SDAA286 March   2026 MSPM0G3519

 

  1.   1
  2.   Abstract
  3.   Trademarks
  4. 1 Introduction
  5. 2 Idle-Low State: PWM Output Channel Low-state Configuration
  6. 3 Asymmetric PWM: Dual Synchronized PWM Generation with Phase Shift Control
    1. 3.1 Using Phase Load Functionality
      1. 3.1.1 Configuration for the Primary Timer (Main Timer)
      2. 3.1.2 Configuration for the Secondary Timer
      3. 3.1.3 Implementation for Cross Trigger Function
    2. 3.2 Using Secondary Capture-Compare Channels
  7. 4 Bit-Banging Emulation: Software-based Communication Protocol Implementation
    1. 4.1 Emulation of UART Rx Using TIMA
    2. 4.2 Emulation of UART Tx Using TIMA
  8. 5 Feedback-Based PWM Generation
    1. 5.1 Feedback-Based PWM Signal Replication
    2. 5.2 Delayed PWM Signal Generation Using an Input Reference
  9. 6 Delayed Timer Start: Synchronized Timer Instances Initiation with Configurable Delays
  10. 7 Stopping a Running Timer Based on Hardware Events
  11. 8 Dynamic PWM Update: Duty Cycle and Time Period Adjustment
    1. 8.1 Shadow Load and Shadow Compare Features
    2. 8.2 Arbitrary Signal Generation with DMA
  12. 9 Summary
  13. 10References
Application Note

Advanced Timer Techniques in MSPM0