SLYT837 January   2023 TPS543B22 , TPS548A28 , TPS56121


  1. Introduction
  2. Selecting and bounding the application
  3. Designing the second-stage filter
  4. Voltage-mode control architecture
  5. D-CAP3 control architecture
  6. Advanced current mode (ACM) control architecture
  7. Efficiency penalty
  8. Conclusion
  9. References
  10. 10Related Websites


Advanced processors and system-on-chip (SoC) with integrated point-to-point serial communication or an analog front end (AFE) require a power supply with low output-voltage ripple to maintain signal integrity and improve performance. The output-voltage ripple requirement of the processor’s point-of-load (POL) power supply can be below 2-mV, which is about one-tenth of the ripple for a typical design, putting heavy design constraint on the synchronous buck converter. Since the processor’s output current requirements exceed the capabilities of a linear post-regulator, employing a second-stage filter, a higher switching frequency and additional output capacitance greatly reduce the POL’s ripple. Synchronous-buck converters are available with several different control architectures, each having a unique method to ensure stability when designing for low-ripple voltage. This article compares three different control architectures: externally-compensated voltage-mode, constant on-time and selectable-compensation current-mode to achieve 1-mV output voltage ripple complete with test data using the same electrical specifications and comparison of output voltage ripple, solution size, load transients and efficiency.