SNAS522J September   2011  – March 2018 LMK03806

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
    1.     Device Images
      1.      Functional Block Diagram
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Differential Voltage Measurement Terminology
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagrams
    3. 8.3 Features Description
      1. 8.3.1 Serial MICROWIRE Timing Diagram and Terminology
      2. 8.3.2 Crystal Support With Buffered Outputs
      3. 8.3.3 Integrated Loop Filter Poles
      4. 8.3.4 Integrated VCO
      5. 8.3.5 Clock Distribution
        1. 8.3.5.1 CLKout DIvider
        2. 8.3.5.2 Programmable Output Type
        3. 8.3.5.3 Clock Output Synchronization
      6. 8.3.6 Default Start-Up Clocks
    4. 8.4 Device Functional Modes
    5. 8.5 Programming
      1. 8.5.1 General Information
        1. 8.5.1.1 Special Programming Case for R0 to R5 for CLKoutX_Y_DIV > 25
        2. 8.5.1.2 Recommended Initial Programming Sequence
        3. 8.5.1.3 READBACK
          1. 8.5.1.3.1 Readback Example
    6. 8.6 Register Maps
      1. 8.6.1  Default Device Register Settings After Power On Reset
      2. 8.6.2  Register R0 TO R5
        1. 8.6.2.1 CLKoutX_Y_PD, Powerdown CLKoutX_Y Output Path
        2. 8.6.2.2 RESET
        3. 8.6.2.3 POWERDOWN
        4. 8.6.2.4 CLKoutX_Y_DIV, Clock Output Divide
      3. 8.6.3  Registers R6 TO R8
        1. 8.6.3.1 CLKoutX_TYPE
      4. 8.6.4  REGISTER R9
      5. 8.6.5  REGISTER R10
        1. 8.6.5.1 OSCout1_TYPE, LVPECL Output Amplitude Control
        2. 8.6.5.2 OSCout0_TYPE
        3. 8.6.5.3 EN_OSCoutX, OSCout Output Enable
        4. 8.6.5.4 OSCoutX_MUX, Clock Output Mux
        5. 8.6.5.5 OSCout_DIV, Oscillator Output Divide
      6. 8.6.6  REGISTER R11
        1. 8.6.6.1 NO_SYNC_CLKoutX_Y
        2. 8.6.6.2 SYNC_POL_INV
        3. 8.6.6.3 SYNC_TYPE
        4. 8.6.6.4 EN_PLL_XTAL
      7. 8.6.7  REGISTER R12
        1. 8.6.7.1 LD_MUX
        2. 8.6.7.2 LD_TYPE
        3. 8.6.7.3 SYNC_PLL_DLD
      8. 8.6.8  REGISTER R13
        1. 8.6.8.1 READBACK_TYPE
        2. 8.6.8.2 GPout0
      9. 8.6.9  REGISTER 14
        1. 8.6.9.1 GPout1
      10. 8.6.10 REGISTER 16
      11. 8.6.11 REGISTER 24
        1. 8.6.11.1 PLL_C4_LF, PLL Integrated Loop Filter Component
        2. 8.6.11.2 PLL_C3_LF, PLL Integrated Loop Filter Component
        3. 8.6.11.3 PLL_R4_LF, PLL Integrated Loop Filter Component
        4. 8.6.11.4 PLL_R3_LF, PLL Integrated Loop Filter Component
      12. 8.6.12 REGISTER 26
        1. 8.6.12.1 EN_PLL_REF_2X, PLL Reference Frequency Doubler
        2. 8.6.12.2 PLL_CP_GAIN, PLL Charge Pump Current
        3. 8.6.12.3 PLL_DLD_CNT
      13. 8.6.13 REGISTER 28
        1. 8.6.13.1 PLL_R, PLL R Divider
      14. 8.6.14 REGISTER 29
        1. 8.6.14.1 OSCin_FREQ, PLL Oscillator Input Frequency Register
        2. 8.6.14.2 PLL_N_CAL, PLL N Calibration Divider
      15. 8.6.15 REGISTER 30
        1. 8.6.15.1 PLL_P, PLL N Prescaler Divider
        2. 8.6.15.2 PLL_N, PLL N Divider
      16. 8.6.16 REGISTER 31
        1. 8.6.16.1 READBACK_ADDR
        2. 8.6.16.2 uWire_LOCK
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 Crystal Interface
      2. 9.1.2 Driving OSCin Pins With a Single-Ended Source
      3. 9.1.3 Driving OSCin Pins With a Differential Source
      4. 9.1.4 Frequency Planning With the LMK03806
      5. 9.1.5 Configuring the PLL
        1. 9.1.5.1 Example PLL Configuration
      6. 9.1.6 Digital Lock Detect
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Device Selection
          1. 9.2.2.1.1 Clock Architect
          2. 9.2.2.1.2 Clock Design Tool
          3. 9.2.2.1.3 Calculation Using LCM
        2. 9.2.2.2 Device Configuration
        3. 9.2.2.3 PLL Loop Filter Design
          1. 9.2.2.3.1 Example Loop Filter Design
        4. 9.2.2.4 Other Device Specific Configuration
          1. 9.2.2.4.1 Digital Lock Detect
        5. 9.2.2.5 Device Programming
      3. 9.2.3 Application Curves
    3. 9.3 System Examples
      1. 9.3.1 System Level Diagram
    4. 9.4 Do's and Don'ts
      1. 9.4.1 LVCMOS Complementary vs. Non-Complementary Operation
      2. 9.4.2 LVPECL Outputs
      3. 9.4.3 Sharing MICROWIRE (SPI) Lines
      4. 9.4.4 SYNC Pin
  10. 10Power Supply Recommendations
    1. 10.1 Current Consumption and Power Dissipation Calculations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 Related Links
    4. 12.4 Community Resource
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • High Performance, Ultra Low Jitter Clock Generator
  • Low Jitter
    • < 50-fs Jitter (1.875 MHz – 20 MHz) at 312.5-MHz Output Frequency
    • < 150-fs Jitter (12 kHz – 20 MHz) at 312.5-MHz Output Frequency
  • Generates Multiple Clocks from a Low-Cost Crystal or External Clock.
  • 14 Outputs With Programmable Output Format (LVDS, LVPECL, CMOS)
  • Up to 8 Unique Output Frequencies.
  • Industrial Temperature Range: –40 to 85 °C
  • Tunable VCO Frequency from 2.37 – 2.6 GHz
  • Programmable Dividers to Generate Multiple Clocks from a Low Cost Crystal.
  • 3.15-V to 3.45-V Operation