SNAS252S October   2005  – December 2014 LMX2531

PRODUCTION DATA.  

  1. 1 Features
  2. 2 Applications
  3. 3 Description
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 MICROWIRE Timing Requirements
    7. 6.7 Typical Performance Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Reference Oscillator Input
      2. 7.3.2 R Divider
      3. 7.3.3 Phase Detector and Charge Pump
      4. 7.3.4 N Divider and Fractional Circuitry
      5. 7.3.5 Partially Integrated Loop Filter
      6. 7.3.6 Low Noise, Fully Integrated VCO
      7. 7.3.7 Programmable VCO Divider
      8. 7.3.8 Serial Data Timing Requirements
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
    6. 7.6 Register Maps
      1. 7.6.1 General Programming Information
        1. 7.6.1.1  Initialization Sequence
        2. 7.6.1.2  Complete Register Content Map
        3. 7.6.1.3  Register R0
          1. 7.6.1.3.1 NUM[10:0] and NUM[21:12] -- Fractional Numerator
          2. 7.6.1.3.2 N[7:0] and N[10:8]
        4. 7.6.1.4  Register R1
          1. 7.6.1.4.1 NUM[21:12]
          2. 7.6.1.4.2 N[10:8] -- 3 MSB Bits for the N Counter
          3. 7.6.1.4.3 ICP[3:0] -- Charge Pump Current
        5. 7.6.1.5  Register R2
          1. 7.6.1.5.1 R[5:0] -- R Counter Value
          2. 7.6.1.5.2 DEN[21:12] and DEN[11:0]-- Fractional Denominator
        6. 7.6.1.6  Register R3
          1. 7.6.1.6.1 DEN[21:12] -- Extension for the Fractional Denominator
          2. 7.6.1.6.2 FoLD[3:0] -- Multiplexed Output for Ftest/LD Pin
          3. 7.6.1.6.3 ORDER -- Order of Delta-Sigma Modulator
          4. 7.6.1.6.4 DITHER -- Dithering
          5. 7.6.1.6.5 FDM -- Fractional Denominator Mode
          6. 7.6.1.6.6 DIV2
        7. 7.6.1.7  Register R4
          1. 7.6.1.7.1 TOC[13:0] -- Time-Out Counter for FastLock
          2. 7.6.1.7.2 ICPFL[3:0] -- Charge Pump Current for Fastlock
        8. 7.6.1.8  Register R5
          1. 7.6.1.8.1 EN_PLL -- Enable Bit for PLL
          2. 7.6.1.8.2 EN_VCO -- Enable Bit for the VCO
          3. 7.6.1.8.3 EN_OSC -- Enable Bit for the Oscillator Inverter
          4. 7.6.1.8.4 EN_VCOLDO -- Enable Bit for the VCO LDO
          5. 7.6.1.8.5 EN_PLLLDO1 -- Enable Bit for the PLL LDO 1
          6. 7.6.1.8.6 EN_PLLLDO2 -- Enable Bit for the PLL LDO 2
          7. 7.6.1.8.7 EN_DIGLDO -- Enable Bit for the digital LDO
          8. 7.6.1.8.8 REG_RST -- Resets All Registers to Default Settings
        9. 7.6.1.9  Register R6
          1. 7.6.1.9.1 C3_C4_ADJ[2:0] -- Value FOR C3 and C4 In The Internal Loop Filter
          2. 7.6.1.9.2 R3_ADJ_FL[1:0] -- Value for Internal Loop Filter Resistor R3 During Fastlock
          3. 7.6.1.9.3 R3_ADJ[1:0] -- Value for Internal Loop Filter Resistor R3
          4. 7.6.1.9.4 R4_ADJ_FL[1:0] -- Value for Internal Loop Filter Resistor R4 During Fastlock
          5. 7.6.1.9.5 R4_ADJ[1:0] -- Value for Internal Loop Filter Resistor R4
          6. 7.6.1.9.6 EN_LPFLTR-- Enable for Partially Integrated Internal Loop Filter
          7. 7.6.1.9.7 VCO_ACI_SEL
          8. 7.6.1.9.8 XTLSEL[2:0] -- OSCin Select
        10. 7.6.1.10 Register R7
          1. 7.6.1.10.1 XTLDIV[1:0] -- Division Ratio for the OSCin Frequency
          2. 7.6.1.10.2 XTLMAN[11:0] -- Manual OSCin Mode
        11. 7.6.1.11 Register R8
          1. 7.6.1.11.1 XTLMAN2 -- Manual Crystal Mode Second Adjustment
          2. 7.6.1.11.2 LOCKMODE -- Frequency Calibration Mode
        12. 7.6.1.12 Register R9
        13. 7.6.1.13 Register R12
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curves
    3. 8.3 Do's and Don'ts
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 Typical Connection Diagram
        1. 10.1.1.1 VccDIG, VccVCO, VccBUF, and VccPLL
        2. 10.1.1.2 VregDIG
        3. 10.1.1.3 VrefVCO
        4. 10.1.1.4 VregVCO
        5. 10.1.1.5 VregPLL1VregPLL2
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Device Support
    2. 11.2 Trademarks
    3. 11.3 Electrostatic Discharge Caution
    4. 11.4 Glossary
  12. 12Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Features

  • Multiple Frequency Options Available
    • See Device Information Table
    • Frequencies From: 553 MHz to 3132 MHz
  • PLL Features
    • Fractional-N Delta-Sigma Modulator Order Programmable up to Fourth Order
    • FastLock/Cycle Slip Reduction with Timeout Counter
    • Partially Integrated, Adjustable Loop Filter
    • Very Low Phase Noise and Spurs
  • VCO Features
    • Integrated Tank Inductor
    • Low Phase Noise
  • Other Features
    • 2.8-V to 3.2-V Operation
    • Low Operating Current
    • Low Power-Down Current
    • 1.8-V MICROWIRE Support
    • 36-Pin 6-mm × 6-mm × 0.8-mm WQFN Package

2 Applications

  • Cellular Base Stations
  • Wireless LANs
  • Broadband Wireless Access
  • Satellite Communications
  • Wireless Radios
  • Automotive
  • CATV Equipment
  • Instrumentation and Test Equipment
  • RFID Readers
  • Data Converter Clocking

3 Description

The LMX2531 is a low-power, high-performance frequency synthesizer system which includes a fully integrated delta-sigma PLL and VCO with fully integrated tank circuit. The third and fourth poles are also integrated and adjustable. Ultra-low noise and high-precision LDOs are integrated for the PLL and VCO, which yield higher supply-noise immunity and more consistent performance. When combined with a high-quality reference oscillator, the LMX2531 device generates very stable, low-noise local-oscillator signals for up and down conversion in wireless communication devices. The LMX2531 device is a monolithic integrated circuit, fabricated in an advanced BiCMOS process. Several different versions of this product accommodate different frequency bands.

Device Information(1)

PART LOW BAND HIGH BAND
LMX2531LQ1146E 553 — 592 MHz 1106 — 1184 MHz
LMX2531LQ1226E 592 — 634 MHz 1184 — 1268 MHz
LMX2531LQ1312E 634 — 680 MHz 1268 — 1360 MHz
LMX2531LQ1415E 680 — 735 MHz 1360 — 1470 MHz
LMX2531LQ1500E 749.5 — 755 MHz 1499 — 1510 MHz
LMX2531LQ1515E 725 — 790 MHz 1450 — 1580 MHz
LMX2531LQ1570E 765 — 818 MHz 1530 — 1636 MHz
LMX2531LQ1650E 795 — 850 MHz 1590 — 1700 MHz
LMX2531LQ1700E 831 — 885 MHz 1662 — 1770 MHz
LMX2531LQ1742 880 — 933 MHz 1760 — 1866 MHz
LMX2531LQ1778E 863 — 920 MHz 1726 — 1840 MHz
LMX2531LQ1910E 917 — 1014 MHz 1834 — 2028 MHz
LMX2531LQ2080E 952 — 1137 MHz 1904 — 2274 MHz
LMX2531LQ2265E 1089 — 1200 MHz 2178 — 2400 MHz
LMX2531LQ2570E 1168 — 1395 MHz 2336 — 2790 MHz
LMX2531LQ2820E 1355 — 1462 MHz 2710 — 2925 MHz
LMX2531LQ3010E 1455 — 1566 MHz 2910 — 3132 MHz
  1. For all available packages, see the orderable addendum at the end of the datasheet.

Simplified Schematic

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