SNVSCE1B
May 2023 – November 2023
LP5860T
PRODUCTION DATA
1
1
Features
2
Applications
3
Description
4
Device Comparison
5
Pin Configuration and Functions
6
Specifications
6.1
Absolute Maximum Ratings
6.2
ESD Ratings
6.3
Recommended Operating Conditions
6.4
Thermal Information
6.5
Electrical Characteristics
6.6
Timing Requirements
14
6.7
Typical Characteristics
7
Detailed Description
7.1
Overview
7.2
Functional Block Diagram
7.3
Feature Description
7.3.1
Time-Multiplexing Matrix
7.3.2
Analog Dimming (Current Gain Control)
7.3.3
PWM Dimming
7.3.4
ON and OFF Control
7.3.5
Data Refresh Mode
7.3.6
Full Addressable SRAM
7.3.7
Protections and Diagnostics
7.4
Device Functional Modes
7.5
Programming
7.6
Register Maps
8
Application and Implementation
8.1
Application Information
8.2
Typical Application
8.2.1
Application
8.2.2
Design Requirements
8.2.3
Detailed Design Procedure
8.2.3.1
Program Procedure
8.2.4
Application Performance Plots
8.3
Power Supply Recommendations
8.4
Layout
8.4.1
Layout Guidelines
8.4.2
Layout Example
9
Device and Documentation Support
9.1
Receiving Notification of Documentation Updates
9.2
Support Resources
9.3
Trademarks
9.4
Electrostatic Discharge Caution
9.5
Glossary
10
Revision History
11
Mechanical, Packaging, and Orderable Information
Package Options
Mechanical Data (Package|Pins)
RKP|40
MPQF261B
Thermal pad, mechanical data (Package|Pins)
Orderable Information
snvsce1b_oa
snvsce1b_pm
Data Sheet
LP5860T
11
×
18
LED
High-Current
Matrix Driver
with 8-Bit Analog and 8-Bit or 16-Bit PWM Dimming