SPRS948 July   2016 SM320C6457-HIREL


  1. 1Device Overview
    1. 1.1 Features
    2. 1.2 Applications
    3. 1.3 Description
    4. 1.4 Description (continued)
    5. 1.5 Functional Block Diagram
  2. 2Revision History
  3. 3Terminal Configuration and Functions
    1. 3.1 Pin Diagram
    2. 3.2 Pin Attributes
      1. 3.2.1 Pin Map
    3. 3.3 Signal Descriptions
  4. 4Specifications
    1. 4.1 Absolute Maximum Ratings
    2. 4.2 ESD Ratings
    3. 4.3 Recommended Operating Conditions
    4. 4.4 Electrical Characteristics
    5. 4.5 Thermal Resistance Characteristics
    6. 4.6 Timing and Switching Characteristics
      1. 4.6.1 Timing Parameters and Information
        1. 1.8-V Signal Transition Levels
        2. 3.3-V Signal Transition Levels
        3. 3.3-V Signal Transition Rates
        4. Timing Parameters and Board Routing Analysis
      2. 4.6.2 Power Supply Sequencing
        1. Power-Supply Decoupling
        2. Power-Down Operation
        3. Power Supply to Peripheral I/O Mapping
      3. 4.6.3 Reset Timing
      4. 4.6.4 Clock and Control Signal Transition Behavior
    7. 4.7 Peripherals
      1. 4.7.1  Enhanced Direct Memory Access (EDMA3) Controller
        1. EDMA3 Device-Specific Information
        2. EDMA3 Channel Synchronization Events
        3. EDMA3 Peripheral Register Description(s)
      2. 4.7.2  Interrupts
        1. Interrupt Sources and Interrupt Controller
        2. External Interrupts Electrical Data/Timing
      3. 4.7.3  Reset Controller
        1. Power-on Reset (POR Pin)
        2. Warm Reset (RESET Pin)
        3. System Reset
        4. CPU Reset
        5. Reset Priority
        6. Reset Controller Register
          1. Reset Type Status Register
          2. Software Reset Control Register
          3. Reset Configuration Register
      4. 4.7.4  PLL1 and PLL1 Controller
        1. PLL1 Controller Device-Specific Information
          1. Internal Clocks and Maximum Operating Frequencies
          2. PLL1 Controller Operating Modes
          3. PLL1 Stabilization, Lock, and Reset Times
        2. PLL1 Controller Memory Map
        3. PLL1 Controller Registers
          1.  PLL1 Control Register
          2.  PLL Multiplier Control Register
          3.  PLL Post-Divider Control Register
          4.  PLL Controller Divider 3 Register
          5.  PLL Controller Divider 6 Register
          6.  PLL Controller Divider 7 Register
          7.  PLL Controller Divider 8 Register
          8.  PLL Controller Command Register
          9.  PLL Controller Status Register
          10. PLL Controller Clock Align Control Register
          11. PLLDIV Ratio Change Status Register
          12. SYSCLK Status Register
        4. PLL1 Controller Input and Output Electrical Data/Timing
      5. 4.7.5  PLL2
        1. PLL2 Device-Specific Information
          1. Internal Clocks and Maximum Operating Frequencies
          2. PLL2 Operating Modes
        2. PLL2 Input Clock Electrical Data/Timing
      6. 4.7.6  DDR2 Memory Controller
        1. DDR2 Memory Controller Device-Specific Information
        2. DDR2 Memory Controller Peripheral Register Description(s)
        3. DDR2 Memory Controller Electrical Data/Timing
      7. 4.7.7  External Memory Interface A (EMIFA)
        1. EMIFA Device-Specific Information
        2. EMIFA Peripheral Register Description(s)
        3. EMIFA Electrical Data/Timing
          1. AECLKIN and AECLKOUT Timing
          2. Asynchronous Memory Timing
          3. Programmable Synchronous Interface Timing
      8. 4.7.8  I2C Peripheral
        1. I2C Device-Specific Information
        2. I2C Peripheral Register Description(s)
        3. I2C Electrical Data/Timing
          1. Inter-Integrated Circuits (I2C) Timing
      9. 4.7.9  Host-Port Interface (HPI) Peripheral
        1. HPI Device-Specific Information
        2. HPI Peripheral Register Description(s)
        3. HPI Electrical Data/Timing
      10. 4.7.10 Multichannel Buffered Serial Port (McBSP)
        1. McBSP Device-Specific Information
          1. McBSP Peripheral Register Description(s)
        2. McBSP Electrical Data/Timing
      11. 4.7.11 Ethernet MAC (EMAC)
        1. EMAC Device-Specific Information
        2. EMAC Peripheral Register Description(s)
        3. EMAC Electrical Data/Timing (SGMII)
      12. 4.7.12 Management Data Input/Output (MDIO)
        1. MDIO Peripheral Register Description(s)
        2. MDIO Electrical Data/Timing
      13. 4.7.13 Timers
        1. Timers Device-Specific Information
          1. Timer Watchdog Select
        2. Timers Peripheral Register Description(s)
        3. Timers Electrical Data/Timing
      14. 4.7.14 Enhanced Viterbi-Decoder Coprocessor (VCP2)
        1. VCP2 Device-Specific Information
        2. VCP2 Peripheral Register Description
      15. 4.7.15 Enhanced Turbo Decoder Coprocessor (TCP2)
        1. TCP2 Device-Specific Information
      16. 4.7.16 UTOPIA
        1. UTOPIA Device-Specific Information
        2. UTOPIA Peripheral Register Description(s)
        3. UTOPIA Electrical Data/Timing
      17. 4.7.17 Serial RapidIO (SRIO) Port
        1. Serial RapidIO Device-Specific Information
        2. Serial RapidIO Peripheral Register Description(s)
        3. Serial RapidIO Electrical Data/Timing
      18. 4.7.18 General-Purpose Input/Output (GPIO)
        1. GPIO Device-Specific Information
        2. GPIO Peripheral Register Description(s)
        3. GPIO Electrical Data/Timing
      19. 4.7.19 Emulation Features and Capability
        1. Advanced Event Triggering (AET)
        2. Trace
          1. Trace Electrical Data/Timing
        3. IEEE 1149.1 JTAG
          1. IEEE 1149.1 JTAG Compatibility Statement
          2. JTAG Electrical Data/Timing
          3. HS-RTDX Electrical Data/Timing
  5. 5Detailed Description
    1. 5.1 Device Overview
    2. 5.2 CPU (DSP Core) Description
    3. 5.3 C64x+ Megamodule
      1. 5.3.1 Memory Architecture
        1. L1P Memory
        2. L1D Memory
        3. L2 Memory
        4. L3 Memory
      2. 5.3.2 Memory Protection
      3. 5.3.3 Bandwidth Management
      4. 5.3.4 Power-Down Control
      5. 5.3.5 Megamodule Resets
      6. 5.3.6 Megamodule Revision
      7. 5.3.7 C64x+ Megamodule Register Descriptions
    4. 5.4 Memory Map Summary
    5. 5.5 Device Configuration
      1. 5.5.1 Device Configuration at Device Reset
      2. 5.5.2 Peripheral Selection After Device Reset
      3. 5.5.3 Device State Control Registers
      4. 5.5.4 Device Status Register Description
      5. 5.5.5 JTAG ID (JTAGID) Register Description
      6. 5.5.6 Pullup/Pulldown Resistors
    6. 5.6 System Interconnect
      1. 5.6.1 Internal Buses, Bridges, and Switch Fabrics
      2. 5.6.2 Data Switch Fabric Connections
      3. 5.6.3 Configuration Switch Fabric
      4. 5.6.4 Bus Priorities
    7. 5.7 Boot Modes
      1. 5.7.1 Second-Level Bootloaders
      2. 5.7.2 Boot Sequence
    8. 5.8 Rake Search Accelerator (RSA)
  6. 6Device and Documentation Support
    1. 6.1 Device Nomenclature
    2. 6.2 Tools and Software
    3. 6.3 Documentation Support
      1. 6.3.1 Receiving Notification of Documentation Updates
    4. 6.4 Community Resources
    5. 6.5 Trademarks
    6. 6.6 Electrostatic Discharge Caution
    7. 6.7 Glossary
  7. 7Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
  • GMH|688
Thermal pad, mechanical data (Package|Pins)
Orderable Information

1 Device Overview

1.1 Features

  • High-Performance Fixed-Point Digital Signal Processor (DSP) — SM320C6457-HIREL
    • 1.18-ns, 1-ns, and 0.83-ns Instruction Cycle Time
    • 850-MHz and 1-GHz Clock Rate
    • Eight 32-Bit Instructions/Cycle
    • 8000 and 9600 MIPS/MMACS (16 Bit)
    • Extended Case Temperature
      • –55ºC to 100ºC (1 GHz)
  • TMS320C64x+™ DSP Core
    • Dedicated SPLOOP Instruction
    • Compact Instructions (16 Bit)
    • Instruction Set Enhancements
    • Exception Handling
  • TMS320C64x+ Megamodule L1/L2 Memory Architecture:
    • 256K-Bit (32Kb) L1P Program Cache [Direct Mapped]
    • 256K-Bit (32Kb) L1D Data Cache [2-Way Set-Associative]
    • 16M-Bit (2048Kb) L2 Unified Mapped Ram/Cache [Flexible Allocation]
      • Configurable up to 1MB of L2 Cache
    • 512K-Bit (64Kb) L3 ROM
    • Time Stamp Counter
  • Enhanced VCP2
    • Supports Over 694 7.95-Kbps AMR
    • Programmable Code Parameters
  • Two Enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B)
    • Each TCP2 Supports up to Eight 2-Mbps 3GPP (6 Iterations)
    • Programmable Turbo Code and Decoding Parameters
  • Endianess: Little Endian, Big Endian
  • 64-Bit External Memory Interface (EMIFA)
    • Glueless Interface to Asynchronous Memories (SRAM, Flash, and EEPROM) and Synchronous Memories (SBSRAM, ZBT SRAM)
    • Supports Interface to Standard Sync Devices and Custom Logic (FPGA, CPLD, ASICs, and So Forth)
    • 32M-Byte Total Addressable External Memory Space
  • 32-Bit DDR2 Memory Controller (DDR2-667 SDRAM)
  • Four 1× Serial RapidIO® Links (or One 4×), v1.3 Compliant
    • 1.25-, 2.5-, 3.125-Gbps Link Rates
    • Message Passing, DirectIO Support, Error Management Extensions, Congestion Control
    • IEEE 1149.6 Compliant I/Os
  • EDMA3 Controller (64 Independent Channels)
  • 32-/16-Bit Host-Port Interface (HPI)
  • Two 1.8-V McBSPs
  • 10/100/1000 Mb/s Ethernet MAC (EMAC)
    • IEEE 802.3 Compliant
    • Supports SGMII, v1.8 Compliant
    • 8 Independent Transmit (TX) and 8 Independent Receive (RX) Channels
  • Two 64-Bit General-Purpose Timers
    • Configurable as Four 32-Bit Timers
    • Configurable in a Watchdog Timer Mode
    • UTOPIA Level 2 Slave ATM Controller
    • 8-Bit Transmit and Receive Operations up to 50 MHz per Direction
    • User-Defined Cell Format up to 64 Bytes
  • One 1.8-V Inter-Integrated Circuit (I2C) Bus
  • 16 General-Purpose I/O (GPIO) Pins
  • System PLL and PLL Controller
  • DDR PLL, Dedicated to DDR2 Memory Controller
  • Advanced Event Triggering (AET) Compatible
  • Trace-Enabled Device
  • Supports IP Security
  • IEEE-1149.1 and IEEE-1149.6 (JTAG™) Boundary-Scan-Compatible
  • 688-Pin Ball Grid Array (BGA) Package (GMH Suffix), 0.8-mm Ball Pitch
  • 0.065-µm/7-Level Cu Metal Process (CMOS)
  • 3.3-V, 1.8-V, 1.1-V I/Os, 1.1-V and 1.2-V Internal

1.2 Applications

  • Remote Radio Unit
  • Software Defined Radio
  • Voice Processing
  • Biometrics

1.3 Description

The TMS320C64x+™ DSPs (including the SM320C6457-HIREL device) are the highest-performance fixed-point DSP generation in the TMS320C6000™ DSP platform. The SM320C6457-HIREL device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture developed by Texas Instruments (TI), making these DSPs an excellent choice for applications including video and telecom infrastructure, imaging/medical, and wireless infrastructure (WI). The C64x+ devices are upward code-compatible from previous devices that are part of the C6000™ DSP platform.

Based on 65-nm process technology and with performance of up to 9600 million instructions per second (MIPS) [or 9600 16-bit MMACs per cycle] at a 1.2-GHz clock rate, the SM320C6457-HIREL device offers cost-effective solutions to high-performance DSP programming challenges. The SM320C6457-HIREL DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors.

The C64x+ DSP core employs eight functional units, two register files, and two data paths. Like the earlier C6000 devices, two of these eight functional units are multipliers or .M units. Each C64x+ .M unit doubles the multiply throughput versus the C64x core by performing four 16-bit × 16-bit multiply-accumulates (MACs) every clock cycle. Thus, eight 16-bit × 16-bit MACs can be executed every cycle on the C64x+ core. At a 1.2-GHz clock rate, this means 9600 16-bit MMACs can occur every second. Moreover, each multiplier on the C64x+ core can compute one 32-bit × 32-bit MAC or four 8-bit × 8-bit MACs every clock cycle.

The SM320C6457-HIREL device includes Serial RapidIO®. This high-bandwidth peripheral dramatically improves system performance and reduces system cost for applications that include multiple DSPs on a board, such as video and telecom infrastructures and medical/imaging.

The SM320C6457-HIREL DSP integrates a large amount of on-chip memory organized as a two-level memory system. The level-1 (L1) program and data memories on the SM320C6457-HIREL device are 32KB each. This memory can be configured as mapped RAM, cache, or some combination of the two. When configured as cache, L1 program (L1P) is a direct mapped cache whereas L1 data (L1D) is a two-way set associative cache. The level 2 (L2) memory is shared between program and data space and is 2048KB in size. L2 memory can also be configured as mapped RAM, cache, or some combination of the two. L2 is configurable up to 1MB of cache. The C64x+ Megamodule also has a 32-bit peripheral configuration (CFG) port, an internal DMA (IDMA) controller, a system component with reset/boot control, interrupt/exception control, a power-down control, and a free-running 32-bit timer for time stamp.

The peripheral set includes: an inter-integrated circuit bus module (I2C); two multichannel buffered serial ports (McBSPs); an 8-bit Universal Test and Operations PHY Interface for Asynchronous Transfer Mode (ATM) Slave [UTOPIA Slave] port; two 64-bit general-purpose timers (also configurable as four 32-bit timers); a user-configurable 16-bit or 32-bit host-port interface (HPI16/HPI32); a 16-pin general-purpose input/output port (GPIO) with programmable interrupt/event generation modes; an 10/100/1000 Ethernet media access controller (EMAC), which provides an efficient interface between the SM320C6457-HIREL DSP core processor and the network; a management data input/output (MDIO) module (also part of the EMAC) that continuously polls all 32 MDIO addresses in order to enumerate all PHY devices in the system; a glueless external memory interface (64-bit EMIFA), which is capable of interfacing to synchronous and asynchronous peripherals; and a 32-bit DDR2 SDRAM interface.

1.4 Description (continued)

The SM320C6457-HIREL device has three high-performance embedded coprocessors [one enhanced Viterbi Decoder Coprocessor (VCP2) and two enhanced Turbo Decoder Coprocessors (TCP2_A and TCP2_B)] that significantly speed up channel-decoding operations on-chip. The VCP2 operating at CPU clock ÷ 3 can decode more than 694 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The VCP2 supports constraint lengths K = 5, 6, 7, 8, and 9, rates R = 3/4, 1/2, 1/3, 1/4, and 1/5, and flexible polynomials, while generating hard decisions or soft decisions. Each TCP2 operating at CPU clock ÷ 3 can decode up to fifty 384-Kbps or eight 2-Mbps turbo encoded channels (assuming 6 iterations). The TCP2 implements the max*log-map algorithm and is designed to support all polynomials and rates required by Third-Generation Partnership Projects (3GPP and 3GPP2), with fully programmable frame length and turbo interleaver. Decoding parameters such as the number of iterations and stopping criteria are also programmable. Communications between the VCP2/TCP2s and the CPU are carried out through the EDMA3 controller.

The SM320C6457-HIREL device has a complete set of development tools, which includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

Device Information(1)

SM320C6457-HIREL FCBGA (688) 23.00 mm × 23.00 mm
(1) For more information, see Section 7, Mechanical Packaging and Orderable Information.

1.5 Functional Block Diagram

Figure 1-1 Shows the functional block diagram of the SM320C6457-HIREL device.

SM320C6457-HIREL Functional_Block_Diagram_6457.gif Figure 1-1 Functional Block Diagram
(A) Each of the TIMER peripherals (TIMER1 and TIMER0) is configurable as either one 64-bit general-purpose timer or two 32-bit general-purpose timers or a watchdog timer.