SLASET9 October   2019 TAS5825P

PRODUCTION DATA.  

  1. Features
  2. Applications
  3. Description
  4. Revision History
  5. Device Comparison Table
  6. Pin Configuration and Functions
    1.     Pin Functions
  7. Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Timing Requirements
    7. 7.7 Typical Characteristics
      1. 7.7.1 Bridge Tied Load (BTL) Configuration Curves with Hybrid Modulation
      2. 7.7.2 Parallel Bridge Tied Load (PBTL) Configuration With Hybrid Modulation
      3. 7.7.3 Bridge Tied Load (BTL) Configuration Curves with BD Modulation
      4. 7.7.4 Parallel Bridge Tied Load (PBTL) Configuration With BD Modulation
  8. Parameter Measurement Information
  9. Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Power Supplies
      2. 9.3.2 Device Clocking
      3. 9.3.3 Serial Audio Port – Clock Rates
      4. 9.3.4 Clock Halt Auto-recovery
      5. 9.3.5 Sample Rate on the Fly Change
      6. 9.3.6 Serial Audio Port - Data Formats and Bit Depths
      7. 9.3.7 Digital Audio Processing
      8. 9.3.8 Class-D Audio Amplifier
        1. 9.3.8.1 Speaker Amplifier Gain Select
        2. 9.3.8.2 Class D Loop Bandwidth and Switching Frequency Setting
    4. 9.4 Device Functional Modes
      1. 9.4.1 Software Control
      2. 9.4.2 Speaker Amplifier Operating Modes
        1. 9.4.2.1 BTL Mode
        2. 9.4.2.2 PBTL Mode
      3. 9.4.3 Low EMI Modes
        1. 9.4.3.1 Spread Spectrum
        2. 9.4.3.2 Channel to Channel Phase Shift
        3. 9.4.3.3 Multi-Devices PWM Phase Synchronization
          1. 9.4.3.3.1 Phase Synchronization With I2S Clock In Startup Phase
          2. 9.4.3.3.2 Phase Synchronization With GPIO
      4. 9.4.4 Thermal Foldback
      5. 9.4.5 Device State Control
      6. 9.4.6 Device Modulation
        1. 9.4.6.1 BD Modulation
        2. 9.4.6.2 1SPW Modulation
        3. 9.4.6.3 Hybrid Modulation
    5. 9.5 Programming and Control
      1. 9.5.1 I2 C Serial Communication Bus
      2. 9.5.2 I2 C Slave Address
        1. 9.5.2.1 Random Write
        2. 9.5.2.2 Sequential Write
        3. 9.5.2.3 Random Read
        4. 9.5.2.4 Sequential Read
        5. 9.5.2.5 DSP Memory Book, Page and BQ update
        6. 9.5.2.6 Checksum
          1. 9.5.2.6.1 Cyclic Redundancy Check (CRC) Checksum
          2. 9.5.2.6.2 Exclusive or (XOR) Checksum
      3. 9.5.3 Control via Software
        1. 9.5.3.1 Startup Procedures
        2. 9.5.3.2 Shutdown Procedures
        3. 9.5.3.3 Protection and Monitoring
          1. 9.5.3.3.1 Overcurrent Limit (Cycle-By-Cycle)
          2. 9.5.3.3.2 Overcurrent Shutdown (OCSD)
          3. 9.5.3.3.3 DC Detect
    6. 9.6 Register Maps
      1. 9.6.1 CONTROL PORT Registers
        1. 9.6.1.1  RESET_CTRL Register (Offset = 1h) [reset = 0x00]
          1. Table 8. RESET_CTRL Register Field Descriptions
        2. 9.6.1.2  DEVICE_CTRL_1 Register (Offset = 2h) [reset = 0x00]
          1. Table 9. DEVICE_CTRL_1 Register Field Descriptions
        3. 9.6.1.3  DEVICE_CTRL2 Register (Offset = 3h) [reset = 00x10]
          1. Table 10. DEVICE_CTRL2 Register Field Descriptions
        4. 9.6.1.4  I2C_PAGE_AUTO_INC Register (Offset = Fh) [reset = 0x00]
          1. Table 11. I2C_PAGE_AUTO_INC Register Field Descriptions
        5. 9.6.1.5  SIG_CH_CTRL Register (Offset = 28h) [reset = 0x00]
          1. Table 12. SIG_CH_CTRL Register Field Descriptions
        6. 9.6.1.6  CLOCK_DET_CTRL Register (Offset = 29h) [reset = 0x00]
          1. Table 13. CLOCK_DET_CTRL Register Field Descriptions
        7. 9.6.1.7  SDOUT_SEL Register (Offset = 30h) [reset = 0x00]
          1. Table 14. SDOUT_SEL Register Field Descriptions
        8. 9.6.1.8  I2S_CTRL Register (Offset = 31h) [reset = 0x00]
          1. Table 15. I2S_CTRL Register Field Descriptions
        9. 9.6.1.9  SAP_CTRL1 Register (Offset = 33h) [reset = 0x02]
          1. Table 16. SAP_CTRL1 Register Field Descriptions
        10. 9.6.1.10 SAP_CTRL2 Register (Offset = 34h) [reset = 0x00]
          1. Table 17. SAP_CTRL2 Register Field Descriptions
        11. 9.6.1.11 FS_MON Register (Offset = 37h) [reset = 0x00]
          1. Table 18. FS_MON Register Field Descriptions
        12. 9.6.1.12 BCK (SCLK)_MON Register (Offset = 38h) [reset = 0x00]
          1. Table 19. BCK_MON Register Field Descriptions
        13. 9.6.1.13 CLKDET_STATUS Register (Offset = 39h) [reset = 0x00]
          1. Table 20. CLKDET_STATUS Register Field Descriptions
        14. 9.6.1.14 DSP_PGM_MODE Register (Offset = 40h) [reset = 0x01]
          1. Table 21. DSP_PGM_MODE Register Field Descriptions
        15. 9.6.1.15 DSP_CTRL Register (Offset = 46h) [reset = 0x01]
          1. Table 22. DSP_CTRL Register Field Descriptions
        16. 9.6.1.16 DIG_VOL Register (Offset = 4Ch) [reset = 30h]
          1. Table 23. DIG_VOL Register Field Descriptions
        17. 9.6.1.17 DIG_VOL_CTRL1 Register (Offset = 4Eh) [reset = 0x33]
          1. Table 24. DIG_VOL_CTRL1 Register Field Descriptions
        18. 9.6.1.18 DIG_VOL_CTRL2 Register (Offset = 4Fh) [reset = 0x30]
          1. Table 25. DIG_VOL_CTRL2 Register Field Descriptions
        19. 9.6.1.19 AUTO_MUTE_CTRL Register (Offset = 50h) [reset = 0x07]
          1. Table 26. AUTO_MUTE_CTRL Register Field Descriptions
        20. 9.6.1.20 AUTO_MUTE_TIME Register (Offset = 51h) [reset = 0x00]
          1. Table 27. AUTO_MUTE_TIME Register Field Descriptions
        21. 9.6.1.21 ANA_CTRL Register (Offset = 53h) [reset = 0h]
          1. Table 28. ANA_CTRL Register Field Descriptions
        22. 9.6.1.22 AGAIN Register (Offset = 54h) [reset = 0x00]
          1. Table 29. AGAIN Register Field Descriptions
        23. 9.6.1.23 SPI_CLK Register (Offset = 55h) [reset = 0x00]
          1. Table 30. SPI_CLK Register Field Descriptions
        24. 9.6.1.24 EEPROM_CTRL0 Register (Offset = 56h) [reset = 0x00]
          1. Table 31. EEPROM_CTRL0 Register Field Descriptions
        25. 9.6.1.25 EEPROM_RD_CMD Register (Offset = 57h) [reset = 0x03]
          1. Table 32. EEPROM_RD_CMD Register Field Descriptions
        26. 9.6.1.26 EEPROM_ADDR_START0 Register (Offset = 58h) [reset = 0x00]
          1. Table 33. EEPROM_ADDR_START0 Register Field Descriptions
        27. 9.6.1.27 EEPROM_ADDR_START1 Register (Offset = 59h) [reset = 0x00]
          1. Table 34. EEPROM_ADDR_START1 Register Field Descriptions
        28. 9.6.1.28 EEPROM_ADDR_START2 Register (Offset = 5Ah) [reset = 0h]
          1. Table 35. EEPROM_ADDR_START2 Register Field Descriptions
        29. 9.6.1.29 EEPROM_BOOT_STATUS Register (Offset = 5Bh) [reset = 0x00]
          1. Table 36. EEPROM_BOOT_STATUS Register Field Descriptions
        30. 9.6.1.30 BQ_WR_CTRL1 Register (Offset = 5Ch) [reset = 0x000]
          1. Table 37. BQ_WR_CTRL1 Register Field Descriptions
        31. 9.6.1.31 PVDD_ADC Register (Offset = 5Eh) [reset = 0h]
          1. Table 38. PVDD_ADC Register Field Descriptions
        32. 9.6.1.32 GPIO_CTRL Register (Offset = 60h) [reset = 0x00]
          1. Table 39. GPIO_CTRL Register Field Descriptions
        33. 9.6.1.33 GPIO0_SEL Register (Offset = 61h) [reset = 0x00]
          1. Table 40. GPIO0_SEL Register Field Descriptions
        34. 9.6.1.34 GPIO1_SEL Register (Offset = 62h) [reset = 0x00]
          1. Table 41. GPIO1_SEL Register Field Descriptions
        35. 9.6.1.35 GPIO2_SEL Register (Offset = 63h) [reset = 0x00]
          1. Table 42. GPIO2_SEL Register Field Descriptions
        36. 9.6.1.36 GPIO_INPUT_SEL Register (Offset = 64h) [reset = 0x00]
          1. Table 43. GPIO_INPUT_SEL Register Field Descriptions
        37. 9.6.1.37 GPIO_OUT Register (Offset = 65h) [reset = 0x00]
          1. Table 44. GPIO_OUT Register Field Descriptions
        38. 9.6.1.38 GPIO_OUT_INV Register (Offset = 66h) [reset = 0x00]
          1. Table 45. GPIO_OUT_INV Register Field Descriptions
        39. 9.6.1.39 DIE_ID Register (Offset = 67h) [reset = 97h]
          1. Table 46. DIE_ID Register Field Descriptions
        40. 9.6.1.40 POWER_STATE Register (Offset = 68h) [reset = 0x00]
          1. Table 47. POWER_STATE Register Field Descriptions
        41. 9.6.1.41 AUTOMUTE_STATE Register (Offset = 69h) [reset = 0x00]
          1. Table 48. AUTOMUTE_STATE Register Field Descriptions
        42. 9.6.1.42 PHASE_CTRL Register (Offset = 6Ah) [reset = 0]
          1. Table 49. PHASE_CTRL Register Field Descriptions
        43. 9.6.1.43 RAMP_SS_CTRL0 Register (Offset = 6Bh) [reset = 0x00]
          1. Table 50. RAMP_SS_CTRL0 Register Field Descriptions
        44. 9.6.1.44 SS_CTRL1 Register (Offset = 6Ch) [reset = 0x00]
          1. Table 51. SS_CTRL1 Register Field Descriptions
        45. 9.6.1.45 SS_CTRL2 Register (Offset = 6Dh) [reset = 0xA0]
          1. Table 52. SS_CTRL2 Register Field Descriptions
        46. 9.6.1.46 SS_CTRL3 Register (Offset = 6Eh) [reset = 0x11]
          1. Table 53. SS_CTRL3 Register Field Descriptions
        47. 9.6.1.47 SS_CTRL4 Register (Offset = 6Fh) [reset = 0x24]
          1. Table 54. SS_CTRL4 Register Field Descriptions
        48. 9.6.1.48 CHAN_FAULT Register (Offset = 70h) [reset = 0x00]
          1. Table 55. CHAN_FAULT Register Field Descriptions
        49. 9.6.1.49 GLOBAL_FAULT1 Register (Offset = 71h) [reset = 0h]
          1. Table 56. GLOBAL_FAULT1 Register Field Descriptions
        50. 9.6.1.50 GLOBAL_FAULT2 Register (Offset = 72h) [reset = 0h]
          1. Table 57. GLOBAL_FAULT2 Register Field Descriptions
        51. 9.6.1.51 WARNING Register (Offset = 73h) [reset = 0x00]
          1. Table 58. WARNING Register Field Descriptions
        52. 9.6.1.52 PIN_CONTROL1 Register (Offset = 74h) [reset = 0x00]
          1. Table 59. PIN_CONTROL1 Register Field Descriptions
        53. 9.6.1.53 PIN_CONTROL2 Register (Offset = 75h) [reset = 0xF8]
          1. Table 60. PIN_CONTROL2 Register Field Descriptions
        54. 9.6.1.54 MISC_CONTROL Register (Offset = 76h) [reset = 0x00]
          1. Table 61. MISC_CONTROL Register Field Descriptions
        55. 9.6.1.55 CBC_CONTROL Register (Offset = 77h) [reset = 0x00]
          1. Table 62. CBC_CONTROL Register Field Descriptions
        56. 9.6.1.56 FAULT_CLEAR Register (Offset = 78h) [reset = 0x00]
          1. Table 63. FAULT_CLEAR Register Field Descriptions
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Bootstrap Capacitors
      2. 10.1.2 Inductor Selections
      3. 10.1.3 Power Supply Decoupling
      4. 10.1.4 Output EMI Filtering
    2. 10.2 Typical Applications
      1. 10.2.1 2.0 (Stereo BTL) System
      2. 10.2.2 Design Requirements
      3. 10.2.3 Detailed Design procedures
        1. 10.2.3.1 Step One: Hardware Integration
        2. 10.2.3.2 Step Two: Hardware Integration
        3. 10.2.3.3 Step Three: Software Integration
      4. 10.2.4 Application Curves
      5. 10.2.5 MONO (PBTL) Systems
      6. 10.2.6 Application Curves
  11. 11Power Supply Recommendations
    1. 11.1 DVDD Supply
    2. 11.2 PVDD Supply
  12. 12Layout
    1. 12.1 Layout Guidelines
      1. 12.1.1 General Guidelines for Audio Amplifiers
      2. 12.1.2 Importance of PVDD Bypass Capacitor Placement on PVDD Network
      3. 12.1.3 Optimizing Thermal Performance
        1. 12.1.3.1 Device, Copper, and Component Layout
        2. 12.1.3.2 Stencil Pattern
          1. 12.1.3.2.1 PCB footprint and Via Arrangement
          2. 12.1.3.2.2 Solder Stencil
    2. 12.2 Layout Example
  13. 13Device and Documentation Support
    1. 13.1 Device Support
      1. 13.1.1 Device Nomenclature
      2. 13.1.2 Development Support
    2. 13.2 Receiving Notification of Documentation Updates
    3. 13.3 Community Resources
    4. 13.4 Trademarks
    5. 13.5 Electrostatic Discharge Caution
    6. 13.6 Glossary
  14. 14Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information

Features

  • High-efficiency Class-D operation with Hybrid-Pro:
    • Approximately 50% longer battery life compared to fixed supply voltage solutions
    • > 90% Power efficiency, 90 mΩ RDSon
    • Low quiescent current, < 20 mA at 12 V PVDD
  • Supports multiple output configurations:
    • 1 × 53 W, 1.0 Mode (4-Ω, 22 V, THD+N=1%)
    • 1 × 65 W, 1.0 Mode (4-Ω, 22 V, THD+N=10%)
    • 2 × 30 W, 2.0 Mode (8-Ω, 24 V, THD+N=1%)
    • 2 × 38 W, 2.0 Mode (8-Ω, 24 V, THD+N=10%)
  • Excellent audio performance:
    • THD+N ≤ 0.03% at 1 W, 1 kHz, PVDD = 12 V
    • SNR ≥ 110 dB (A-weighted), ICN ≤ 35 µVRMS
  • Flexible audio I/O:
    • Supports 32, 44.1, 48, 88.2, 96 kHz SR
    • Supports I2S, LJ, RJ, TDM format
    • Supports 3-wire digital audio interface
  • Flexible processing features:
    • 3-Band advanced DRC + AGL, 2 × 15 BQs
    • PVDD sensing to avoid clipping distortion while voltage rail drops
    • Up to 4 ms lookahead delay buffer for Hybrid-Pro algorithm audio signal tracking
    • Optional 8 or 16 Hybrid-Pro DC-DC control steps with max 10 ms peak sample hold
  • Flexible power supply configurations:
    • PVDD: 4.5 V to 26.4 V
    • DVDD and I/O: 1.8 V or 3.3 V
  • Excellent integrated self-protection:
    • Over-current error (OCE)
    • Cycle-by-cycle current limit
    • Over-temperature warning (OTW)
    • Over-temperature error (OTE)
    • Under, over-voltage lock-out (UVLO, OVLO)
  • Easy System Integration:
    • I2C Software Control
    • Reduced solution size:
      • Small 5 × 5 mm package
      • Fewer passives required compared to open-loop Class-D devices
      • No bulky electrolytic capacitors or large inductors required for most applications