SLVSGA1A december   2022  – may 2023 TPS65219-Q1

PRODUCTION DATA  

  1.   1
  2. 1 Features
  3. 2 Applications
  4. 3 Description
  5. 4 Revision History
  6. 5 Pin Configuration and Functions
  7. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  System Control Thresholds
    6. 6.6  BUCK1 Converter
    7. 6.7  BUCK2, BUCK3 Converter
    8. 6.8  General Purpose LDOs (LDO1, LDO2)
    9. 6.9  General Purpose LDOs (LDO3, LDO4)
    10. 6.10 GPIOs and multi-function pins (EN/PB/VSENSE, nRSTOUT, nINT, GPO1, GPO2, GPIO, MODE/RESET, MODE/STBY, VSEL_SD/VSEL_DDR)
    11. 6.11 Voltage and Temperature Monitors
    12. 6.12 I2C Interface
    13. 6.13 Typical Characteristics
  8. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Power-Up Sequencing
      2. 7.3.2  Power-Down Sequencing
      3. 7.3.3  Push Button and Enable Input (EN/PB/VSENSE)
      4. 7.3.4  Reset to SoC (nRSTOUT)
      5. 7.3.5  Buck Converters (Buck1, Buck2, and Buck3)
        1. 7.3.5.1 Dual Random Spread Spectrum (DRSS)
      6. 7.3.6  Linear Regulators (LDO1 through LDO4)
      7. 7.3.7  Interrupt Pin (nINT)
      8. 7.3.8  PWM/PFM and Low Power Modes (MODE/STBY)
      9. 7.3.9  PWM/PFM and Reset (MODE/RESET)
      10. 7.3.10 Voltage Select pin (VSEL_SD/VSEL_DDR)
      11. 7.3.11 General Purpose Inputs or Outputs (GPO1, GPO2, and GPIO)
      12. 7.3.12 I2C-Compatible Interface
        1. 7.3.12.1 Data Validity
        2. 7.3.12.2 Start and Stop Conditions
        3. 7.3.12.3 Transferring Data
    4. 7.4 Device Functional Modes
      1. 7.4.1 Modes of Operation
        1. 7.4.1.1 OFF State
        2. 7.4.1.2 INITIALIZE State
        3. 7.4.1.3 ACTIVE State
        4. 7.4.1.4 STBY State
        5. 7.4.1.5 Fault Handling
    5. 7.5 User Registers
    6. 7.6 Device Registers
  9. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Typical Application Example
      2. 8.2.2 Design Requirements
      3. 8.2.3 Detailed Design Procedure
        1. 8.2.3.1 Buck1, Buck2, Buck3 Design Procedure
        2. 8.2.3.2 LDO1, LDO2 Design Procedure
        3. 8.2.3.3 LDO3, LDO4 Design Procedure
        4. 8.2.3.4 VSYS, VDD1P8
        5. 8.2.3.5 Digital Signals Design Procedure
    3. 8.3 Application Curves
    4. 8.4 Power Supply Recommendations
    5. 8.5 Layout
      1. 8.5.1 Layout Guidelines
      2. 8.5.2 Layout Example
  10. 9 Device and Documentation Support
    1. 9.1 Documentation Support
      1. 9.1.1 Related Documentation
    2. 9.2 Receiving Notification of Documentation Updates
    3. 9.3 Support Resources
    4. 9.4 Trademarks
    5. 9.5 Electrostatic Discharge Caution
    6. 9.6 Glossary
  11. 10Mechanical, Packaging, and Orderable Information

Package Options

Mechanical Data (Package|Pins)
Thermal pad, mechanical data (Package|Pins)
Orderable Information
Data Sheet

TPS65219-Q1 Integrated Power Management IC for ARM Cortex—A53 Processors