Product details

Sample rate (max) (Msps) 800, 1600 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2500 Architecture Folding Interpolating SNR (dB) 60.4 ENOB (Bits) 9.7 SFDR (dB) 74.3 Operating temperature range (°C) -40 to 85 Input buffer Yes
Sample rate (max) (Msps) 800, 1600 Resolution (Bits) 12 Number of input channels 1, 2 Interface type Parallel LVDS Analog input BW (MHz) 2700 Features Low Power Rating Catalog Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 2500 Architecture Folding Interpolating SNR (dB) 60.4 ENOB (Bits) 9.7 SFDR (dB) 74.3 Operating temperature range (°C) -40 to 85 Input buffer Yes
PBGA (NXA) 292 729 mm² (27 mm × 27 mm)
  • Excellent Noise and Linearity up to and Above fIN = 2.7 GHz
  • Configurable to Either 1.6/1.0 GSPS Interleaved or 800/500 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible with ADC1xD1x00
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution 12 Bits
    • Interleaved 1.6/1.0 GSPS ADCIMD3 (Fin = 2.7GHz @ -13dBFS): -63/-61 dBc (typ)IMD3 (Fin = 2.7GHz @ -16dBFS): -71/-69 dBc (typ)Noise Floor: -152.2/-150.5 dBm/Hz (typ)Noise Power Ratio: 50.4/50.7 dB (typ)Power: 2.50/2.02 W (typ)
    • Dual 800/500 MSPS ADC, Fin = 498 MHzENOB: 9.5/9.6 Bits (typ)SNR: 59.7/59.7 dB (typ)SFDR: 71.2/72 dBc (typ)Power per Channel: 1.25/1.01 W (typ)

All trademarks are the property of their respective owners.

  • Excellent Noise and Linearity up to and Above fIN = 2.7 GHz
  • Configurable to Either 1.6/1.0 GSPS Interleaved or 800/500 MSPS Dual ADC
  • New DESCLKIQ Mode for High Bandwidth, High Sampling Rate Apps
  • Pin-Compatible with ADC1xD1x00
  • AutoSync Feature for Multi-Chip Synchronization
  • Internally Terminated, Buffered, Differential Analog Inputs
  • Interleaved Timing Automatic and Manual Skew Adjust
  • Test Patterns at Output for System Debug
  • Time Stamp Feature to Capture External Trigger
  • Programmable Gain, Offset, and tAD Adjust Feature
  • 1:1 Non-Demuxed or 1:2 Demuxed LVDS Outputs
  • Key Specifications
    • Resolution 12 Bits
    • Interleaved 1.6/1.0 GSPS ADCIMD3 (Fin = 2.7GHz @ -13dBFS): -63/-61 dBc (typ)IMD3 (Fin = 2.7GHz @ -16dBFS): -71/-69 dBc (typ)Noise Floor: -152.2/-150.5 dBm/Hz (typ)Noise Power Ratio: 50.4/50.7 dB (typ)Power: 2.50/2.02 W (typ)
    • Dual 800/500 MSPS ADC, Fin = 498 MHzENOB: 9.5/9.6 Bits (typ)SNR: 59.7/59.7 dB (typ)SFDR: 71.2/72 dBc (typ)Power per Channel: 1.25/1.01 W (typ)

All trademarks are the property of their respective owners.

The 12-bit 1.6/1.0 GSPS ADC12D800/500RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D800/500RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 7th Nyquist zone

The ADC12D800/500RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

The 12-bit 1.6/1.0 GSPS ADC12D800/500RF is an RF-sampling GSPS ADC that can directly sample input frequencies up to and above 2.7 GHz. The ADC12D800/500RF augments the very large Nyquist zone of TI’s GSPS ADCs with excellent noise and linearity performance at RF frequencies, extending its usable range beyond the 7th Nyquist zone

The ADC12D800/500RF provides a flexible LVDS interface which has multiple SPI programmable options to facilitate board design and FPGA/ASIC data capture. The LVDS outputs are compatible with IEEE 1596.3-1996 and supports programmable common mode voltage. The product is packaged in a lead-free 292-ball thermally enhanced BGA package over the rated industrial temperature range of -40°C to +85°C.

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Technical documentation

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* Data sheet ADC12D800/500RF 12-Bit, 1.6/1.0 GSPS RF Sampling ADC datasheet (Rev. E) Mar 25, 2013
Application note AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G) Feb 3, 2017
Application note Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAs Aug 6, 2014
Application note Maximizing SFDR Performance in the GSPS ADC: Spur Sources and Methods of Mitigat Dec 9, 2013
User guide Schematic and Layout Recommendations for the GSPS ADC Apr 29, 2013
Application note AN-2177 Using the LMH6554 as a ADC Driver (Rev. A) Apr 26, 2013
Application note From Sample Instant to Data Output: Understanding Latency in the GSPS ADC Dec 18, 2012
Product overview ADC12Dxx00RF Direct RF-Sampling ADC Family May 16, 2012

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

ADC-LD-BB — ADC low-distortion balun board

One ADC-LD-BB board is included in the hardware kit with the GSPS analog-to-digital converter (ADC) reference boards. Since the analog inputs to the ADC1xDxx00RB are differential and most signal sources are single ended, these balun boards are generally used to achieve (...)

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Support software

WAVEVISION5 — WaveVision 5 Software

WaveVision 5 software is part of the WaveVision evaluation system that also includes WaveVision 5 Data Capture Board. The WaveVision 5 system is an easy-to-use data acquisition and analysis tool, designed to help users evaluate Texas Instruments' Signal Path solutions.

While WaveVision 5 software (...)

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Simulation model

ADC12D1000 IBIS Model

SNAM014.ZIP (41 KB) - IBIS model
Supported products & hardware
Reference design

TIDA-00071 — Schematic and Layout Recommendations for the Giga Sample Per Second (GSPS) ADC

This reference design is a guide to the schematics and layout for the system designer using a GSPS ADC in their system. Use this reference design along with the datasheet — the datasheet is always the final authority. Also, the ADC1xDxxxx(RF)RB Reference Board provides a useful reference (...)

Supported products & hardware
Reference design

TIDA-00113 — Driving GSPS ADCs in Single-Channel or Dual-Channel Mode for High Bandwidth Applications

This design is intended to help the system designer in understanding tradeoffs and optimizing implementation for driving the Giga-Sample-Per-Second ADC with balun configurations for wideband applications.  The tradeoffs considered include balun construction, insertion loss, dynamic (...)

Supported products & hardware
Reference design

TIDA-00479 — Optimal Clock Sources for GSPS ADCs Reference Design

The ADC12D1600RFRB reference design provides a platform to demonstrate a high speed digitizer application which incorporates clocking, power management, and signal processing. The reference design utilizes the 1.6 GSPS ADC12D1600RF device, onboard FPGA Xilinx Virtex 4, and high performance clock (...)

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PBGA (NXA) 292 Ultra Librarian

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