CD74ACT541

ACTIVE

Octal Non-Inverting Buffers/Line Drivers with 3-State Outputs

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Product details

Parameters

Technology Family ACT VCC (Min) (V) 4.5 VCC (Max) (V) 5.5 Channels (#) 8 IOL (Max) (mA) 24 ICC (Max) (uA) 160 IOH (Max) (mA) -24 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Very high speed (tpd 5-10ns), Input clamp diode Data rate (Mbps) 180 Rating Catalog open-in-new Find other Non-Inverting buffer/driver

Package | Pins | Size

PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3 SSOP (DB) 20 38 mm² 5.3 x 7.2 open-in-new Find other Non-Inverting buffer/driver

Features

  • Buffered inputs
  • Typical propagation delay:
    4.5 ns @ VCC = 5 V, TA = 25°C, CL = 50 pF
  • Exceeds 2-kV ESD Protection - MIL-STD-883, Method 3015
  • SCR-Latchup-resistant CMOS process and circuit design
  • Speed of bipolar FAST®/AS/S with significantly reduced power consumption
  • Balanced propagation delays
  • AC types feature 1.5-V to 5.5-V operation and balanced noise immunity at 30% of the supply
  • ± 24-mA output drive current
    -Fanout to 15 FAST® ICs
    -Drives 50-ohm transmission lines
  • Characterized for operation from –40° to 85°C

FAST is a Registered Trademark of Fairchild Semiconductor Corp.

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Description

The CD54/74AC540, –541, and CD54/74ACT540, –541 octal buffer/line drivers use the RCA ADVANCED CMOS technology. The CD54/74AC/ACT540 are inverting 3-state buffers having two active-LOW output enables. The CD54/74AC/ACT541 are non-inverting 3-state buffers having two active-LOW output enables.

The CD74AC540, –541, and CD74ACT540, –541 are supplied in 20-lead dual-in-line plastic packages (E suffix) and in 20-lead dual-in-line small-outline plastic packages (M suffix). Both package types are operable over the following temperature ranges: Industrial (–40 to +85°C) and Extended Industrial/Military (–55 to +125°C).

The CD54AC540, –541, and CD54ACT540, –541, available in chip form (H suffix), are operable over the –55 to +125°C temperature range.

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Technical documentation

= Top documentation for this product selected by TI
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Type Title Date
* Datasheet Octal Buffer/Line Drivers, 3-State datasheet (Rev. A) Nov. 16, 1999
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
10
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

Design tools & simulation

SIMULATION MODELS Download
SCHM060.ZIP (7 KB) - PSpice Model

CAD/CAE symbols

Package Pins Download
PDIP (N) 20 View options
SOIC (DW) 20 View options
SSOP (DB) 20 View options

Ordering & quality

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