Product details

Technology Family HCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 6 ICC (Max) (uA) 160 IOH (Max) (mA) -6 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Input clamp diode Rating Catalog
Technology Family HCT Supply voltage (Min) (V) 4.5 Supply voltage (Max) (V) 5.5 Number of channels (#) 8 IOL (Max) (mA) 6 ICC (Max) (uA) 160 IOH (Max) (mA) -6 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, High speed (tpd 10-50ns), Input clamp diode Rating Catalog
PDIP (N) 20 229 mm² 24.33 x 9.4 SOIC (DW) 20 132 mm² 12.8 x 10.3
  • ’HC540, CD74HCT540: inverting
  • ’HC541, ’HCT541: non-inverting
  • Buffered inputs
  • Three-state outputs
  • Bus line driving capability
  • Typical propagation delay = 9 ns at VCC = 5 V, CL = 15 pF, TA = 25℃
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types
    • 2 V to 6 V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5 V to 5.5 V operation
    • Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min)
    • CMOS input compatibility, II ≤ 1 µA at VOL, VOH
  • ’HC540, CD74HCT540: inverting
  • ’HC541, ’HCT541: non-inverting
  • Buffered inputs
  • Three-state outputs
  • Bus line driving capability
  • Typical propagation delay = 9 ns at VCC = 5 V, CL = 15 pF, TA = 25℃
  • Fanout (over temperature range)
    • Standard outputs: 10 LSTTL loads
    • Bus driver outputs: 15 LSTTL loads
  • Wide operating temperature range: –55℃ to 125℃
  • Balanced propagation delay and transition times
  • Significant power reduction compared to LSTTL Logic ICs
  • HC types
    • 2 V to 6 V operation
    • High noise immunity: NIL = 30%, NIH = 30% of VCC at VCC = 5 V
  • HCT types
    • 4.5 V to 5.5 V operation
    • Direct LSTTL input logic compatibility, VIL = 0.8 V (max), VIH = 2 V (min)
    • CMOS input compatibility, II ≤ 1 µA at VOL, VOH
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Technical documentation

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Type Title Date
* Data sheet CDx4HC(T)541 High-Speed CMOS Logic Octal Buffer and Line Drivers, Three-State datasheet (Rev. D) PDF | HTML 25 Jan 2022
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Logic Cross-Reference (Rev. A) 07 Oct 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
Application note Designing With Logic (Rev. C) 01 Jun 1997
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 01 May 1996
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 01 Apr 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

14-24-LOGIC-EVM — Generic Logic EVM Supporting 14 through 24 Pin PW, DB, D, DW, NS, DYY, and DGV Packages

This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, DYY or DGV package in a 14 to 24 pin count.

User guide: PDF | HTML
Not available on TI.com
Simulation model

CD74HCT541 Behavioral SPICE Model

SCHM113.ZIP (7 KB) - PSpice Model
Package Pins Download
PDIP (N) 20 View options
SOIC (DW) 20 View options

Ordering & quality

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