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Product details

Parameters

Configuration 4:1 Number of channels (#) 2 Power supply voltage - single (V) 1.8, 2.5, 3.3, 5 Ron (Typ) (Ohms) 40 ON-state leakage current (Max) (µA) 1 Bandwidth (MHz) 200 Operating temperature range (C) -55 to 125 Features Break-before-make Input/output continuous current (Max) (mA) 25 Rating Catalog CON (Typ) (pF) 12 open-in-new Find other Analog switches/muxes

Package | Pins | Size

PDIP (N) 16 181 mm² 19.3 x 9.4 SOIC (D) 16 59 mm² 9.9 x 6 SOP (NS) 16 80 mm² 10.2 x 7.8 TSSOP (PW) 16 22 mm² 5 x 4.4 TSSOP (PW) 16 22 mm² 4.4 x 5 open-in-new Find other Analog switches/muxes

Features

  • Wide Analog Input Voltage Range: ±5-V Maximum
  • Low ON-Resistance
    • 70-Ω Typical (VCC – VEE = 4.5 V)
    • 40-Ω Typical (VCC – VEE = 9 V)
  • Low Crosstalk Between Switches
  • Fast Switching and Propagation Speeds
  • Break-Before-Make Switching
  • Wide Operating Temperature Range:
    –55°C to +125°C
  • CD54HC and CD74HC Types
    • Operation Control Voltage: 2 V to 6 V
    • Switch Voltage: 0 V to 10 V
  • CD54HCT and CD74HCT Types
    • Operation Control Voltage: 4.5 V to 5.5 V
    • Switch Voltage: 0 V to 10 V
    • Direct LSTTL Input Logic Compatibility
      VIL = 0.8-V Max, VIH = 2-V Min
    • CMOS Input Compatibility
      II  ≤ 1 µA at VOL, VOH
  • On Products Compliant to MIL-PRF-38535,
    All Parameters Are Tested Unless Otherwise Noted. On All Other Products, Production Processing Does Not Necessarily Include Testing of All Parameters.

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Description

The CDx4HC405x and CDx4HCT405x devices are digitally controlled analog switches that use silicon gate CMOS technology to achieve operating speeds similar to LSTTL with the low-power consumption of standard CMOS integrated circuits.

These analog multiplexers and demultiplexers control analog voltages that may vary across the voltage supply range (for example, VCC to VEE). They are bidirectional switches that allow any analog input to be used as an output and vice versa. The switches have low ON resistance and low OFF leakages. In addition, all these devices have an enable control that, when high, disables all switches to their OFF state.

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Technical documentation

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Type Title Date
* Datasheet CDx4HC405x, CDx4HCT405x High-Speed CMOS Logic Analog Multiplexers and Demultiplexers datasheet (Rev. M) May 22, 2019
Application notes Selecting the Right Texas Instruments Signal Switch (Rev. B) Apr. 02, 2020
Application notes Multiplexers and Signal Switches Glossary Mar. 06, 2020
Technical articles Roll with the design punches and overcome power-sequencing challenges Jul. 29, 2019
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
User guides Signal Switch Data Book (Rev. A) Nov. 14, 2003
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Designing With Logic (Rev. C) Jun. 01, 1997
Application notes Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application notes Live Insertion Oct. 01, 1996
Application notes SN54/74HCT CMOS Logic Family Applications and Restrictions May 01, 1996
Application notes Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc Apr. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

INTERFACE ADAPTERS Download
document-generic User guide
10
Description

The EVM-LEADED1 board allows for quick testing and bread boarding of TI's common leaded packages.  The board has footprints to convert TI's D, DBQ, DCT,DCU, DDF, DGS, DGV, and PW surface mount packages to 100mil DIP headers.     

Features
  • Quick testing of TI's leaded surface mount packages 
  • Allows leaded suface mount packages to be plugged into 100mil spaced bread board 
  • Supports TI's 8 most popular leaded packages with a single panel


CAD/CAE symbols

Package Pins Download
PDIP (N) 16 View options
SO (NS) 16 View options
SOIC (D) 16 View options
TSSOP (PW) 16 View options

Ordering & quality

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