40-pin (RHA) package image

CDCVF857RHAT ACTIVE

2.5-V phase lock loop DDR clock driver

ACTIVE custom-reels CUSTOM Custom reel may be available

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Quality information

Rating Catalog
RoHS Yes
REACH Yes
Lead finish / Ball material NIPDAU
MSL rating / Peak reflow Level-3-260C-168 HR
Quality, reliability
& packaging information

Information included:

  • RoHS
  • REACH
  • Device marking
  • Lead finish / Ball material
  • MSL rating / Peak reflow
  • MTBF/FIT estimates
  • Material content
  • Qualification summary
  • Ongoing reliability monitoring
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Additional manufacturing information

Information included:

  • Fab location
  • Assembly location
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Export classification

*For reference only

  • US ECCN: EAR99

Packaging information

Package | Pins VQFN (RHA) | 40
Operating temperature range (°C) -40 to 85
Package qty | Carrier 250 | SMALL T&R

Features for the CDCVF857

  • Spread-Spectrum Clock Compatible
  • Operating Frequency: 60 MHz to 220 MHz
  • Low Jitter (Cycle-Cycle): ±35 ps
  • Low Static Phase Offset: ±50 ps
  • Low Jitter (Period): ±30 ps
  • 1-to-10 Differential Clock Distribution (SSTL2)
  • Best in Class for VOX = VDD/2 ±0.1 V
  • Operates From Dual 2.6-V or 2.5-V Supplies
  • Available in a 40-Pin MLF Package, 48-Pin TSSOP Package, 56-Ball MicroStar Junior™ BGA Package
  • Consumes < 100-µA Quiescent Current
  • External Feedback Pins (FBIN, FBIN) Are Used to Synchronize the Outputs to the Input Clocks
  • Meets/Exceeds JEDEC Standard (JESD82-1) For DDRI-200/266/333 Specification
  • Meets/Exceeds Proposed DDRI-400 Specification (JESD82-1A)
  • Enters Low-Power Mode When No CLK Input Signal Is Applied or PWRDWN Is Low
  • APPLICATIONS
    • DDR Memory Modules (DDR400/333/266/200)
    • Zero-Delay Fan-Out Buffer

MicroStar Junior is a trademark of Texas Instruments.

Description for the CDCVF857

The CDCVF857 is a high-performance, low-skew, low-jitter, zero-delay buffer that distributes a differential clock input pair (CLK, CLK) to 10 differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). The clock outputs are controlled by the clock inputs (CLK, CLK), the feedback clocks (FBIN, FBIN), and the analog power input (AVDD). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high-impedance state (3-state) and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20 MHz (typical 10 MHz). An input frequency detection circuit detects the low frequency condition and, after applying a >20-MHz input signal, this detection circuit turns the PLL on and enables the outputs.

When AVDD is strapped low, the PLL is turned off and bypassed for test purposes. The CDCVF857 is also able to track spread spectrum clocking for reduced EMI.

Because the CDCVF857 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. The CDCVF857 is characterized for both commercial and industrial temperature ranges.

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Carrier options

You can choose different carrier options based on the quantity of parts, including full reel, custom reel, cut tape, tube or tray.

A custom reel is a continuous length of cut tape from one reel to maintain lot- and date-code traceability, built to the exact quantity requested. Following industry standards, a brass shim connects an 18-inch leader and trailer on both sides of the cut tape for direct feeding into automated assembly machines. TI includes a reeling fee for custom reel orders.

Cut tape is a length of tape cut from a reel. TI may fulfill orders using multiple strips of cut tapes or boxes to satisfy the quantity requested.

TI often ships tube or tray devices inside a box or in the tube or tray, depending on inventory availability. We pack all tapes, tubes or sample boxes according to internal electrostatic discharge and moisture-sensitivity-level protection requirements.

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Lot and date code selection may be available

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