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Product details

Parameters

Number of channels (#) 2 Supply voltage (Min) (V) 4.75 Supply voltage (Max) (V) 5.25 Technology Family LS Input type Bipolar Output type Push-Pull ICC (uA) 20000 IOL (Max) (mA) 4 IOH (Max) (mA) -0.4 Features Standard speed (tpd > 50ns), Retriggerable open-in-new Find other Monostable multivibrator (one-shot)

Package | Pins | Size

CDIP (J) 16 135 mm² 19.65 x 6.92 CFP (W) 16 69 mm² 10 x 6.7 LCCC (FK) 20 79 mm² 8.89 x 8.89 open-in-new Find other Monostable multivibrator (one-shot)

Features

  • D-C Triggered from Active-High or Active-Low Gated Logic Inputs
  • Retriggerable for Very Long Output Pulses, Up to 100% Duty Cycle
  • Overriding Clear Terminates Output Pulse
  • '122 and 'LS122 Have Internal Timing Resistors
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Description

These d-c triggered multivibrators feature output pulse-duration control by three methods. The basic pulse time is programmed by selection of external resistance and capacitance values (see typical application data). The '122 and 'LS122 have internal timing resistors that allow the circuits to be used with only an external capacitor, if so desired. Once triggered, the basic pulse duration may be extended by retriggering the gated low-level-active (A) or high-level-active (B) inputs, or be reduced by use of the overriding clear. Figure 1 illustrates pulse control by retriggering and early clear.

The 'LS122 and 'LS123 are provided enough Schmitt hysteresis to ensure jitter-free triggering from the B input with transition rates as slow as 0.1 millivolt per nanosecond.

The Rint is nominally 10 k for '122 and 'LS122.

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Technical documentation

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Type Title Date
* Data sheet Retriggerable Monostable Multivibrators datasheet Dec. 01, 1983
* SMD SN54LS123 SMD 7603901EA Jun. 21, 2016
Application note Designing With the SN74LVC1G123 Monostable Multivibrator (Rev. A) Mar. 13, 2020
Selection guide Logic Guide (Rev. AB) Jun. 12, 2017
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
User guide LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application note TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
Application note Designing With Logic (Rev. C) Jun. 01, 1997
Application note Designing with the SN54/74LS123 (Rev. A) Mar. 01, 1997
Application note Input and Output Characteristics of Digital Integrated Circuits Oct. 01, 1996
Application note Live Insertion Oct. 01, 1996

Design & development

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CAD/CAE symbols

Package Pins Download
CDIP (J) 16 View options
CFP (W) 16 View options
LCCC (FK) 20 View options

Ordering & quality

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