SN74AHC1G08

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1-ch, 2-input 2-V to 5.5-V high-speed (9 ns) AND gate

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Data sheet

document-pdfAcrobat SN74AHC1G08 Single 2-Input Positive-AND Gate datasheet (Rev. R) PDF | HTML

SN74AHC1G08

ACTIVE

Data sheet

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Product details

Technology family

AHC

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

8

IOH (max) (mA)

-8

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

110

Rating

Catalog

Operating temperature range (°C)

-55 to 125

Technology family

AHC

Number of channels

1

Inputs per channel

2

IOL (max) (mA)

8

IOH (max) (mA)

-8

Input type

Standard CMOS

Output type

Push-Pull

Features

Over-voltage tolerant inputs, Very high speed (tpd 5-10ns)

Data rate (max) (Mbps)

110

Rating

Catalog

Operating temperature range (°C)

-55 to 125

SOT-SC70 (DCK)

5

4.2 mm² (2 mm × 2.1 mm)

SOT-5X3 (DRL)

5

2.56 mm² (1.6 mm × 1.6 mm)

SOT-23 (DBV)

5

8.12 mm² (2.9 mm × 2.8 mm)

Operating Range 2 V to 5.5 V
Maximum tpd of 7 ns at 5 V
Low Power Consumption, 10-µA Maximum ICC
±8-mA Output Drive at 5 V
Schmitt-Trigger Action at All Inputs Makes the Circuit Tolerant for Slower Input Rise and Fall Time
Latch-Up Performance Exceeds 250 mA Per JESD 17

Operating Range 2 V to 5.5 V
Maximum tpd of 7 ns at 5 V
Low Power Consumption, 10-µA Maximum ICC
±8-mA Output Drive at 5 V
Schmitt-Trigger Action at All Inputs Makes the Circuit Tolerant for Slower Input Rise and Fall Time
Latch-Up Performance Exceeds 250 mA Per JESD 17

The SN74AHC1G08 device is a single 2-input positive-AND gate. The device performs the Boolean function Y = A ● B or Y = A + B in positive logic.

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SN74LVC1G08

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1-ch, 2-input 1.65-V to 5.5-V 32 mA drive strength AND gate Voltage range 1.65V to 5.5V, average propagation delay 5.5ns, average drive strength 24mA

Technical documentation

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Top documentation	Type	Title	Format options	Date
*	Data sheet	SN74AHC1G08 Single 2-Input Positive-AND Gate datasheet (Rev. R)	PDF \| HTML	Jan 31, 2024
	Application brief	Optimizing Optical Network Terminal Units With Logic	PDF \| HTML	Apr 5, 2023

Design & development

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Simulation model