Product details

Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (MBits) 100 Rating Catalog Operating temperature range (°C) -40 to 125, -40 to 85
Technology family LVC Supply voltage (min) (V) 1.65 Supply voltage (max) (V) 5.5 Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Ultra high speed (tpd <5ns) Data rate (max) (MBits) 100 Rating Catalog Operating temperature range (°C) -40 to 125, -40 to 85
DSBGA (YZP) 5 2.1875 mm² 1.75 x 1.25 SOT-23 (DBV) 5 8.12 mm² 2.9 x 2.8 SOT-5X3 (DRL) 5 2.56 mm² 1.6 x 1.6 SOT-SC70 (DCK) 5 2.5 mm² 2 x 1.25 USON (DRY) 6 1.45 mm² 1.45 x 1 X2SON (DPW) 5 0.64 mm² 0.8 x 0.8 X2SON (DSF) 6 1 mm² 1 x 1
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Ultra Small 0.64-mm2
    Package (DPW) With 0.5-mm Pitch
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Provides Down Translation to VCC
  • Max tpd of 3.6 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back Drive Protection
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G08 device performs the Boolean function or in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G08 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

This single 2-input positive-AND gate is designed for 1.65-V to 5.5-V VCC operation.

The SN74LVC1G08 device performs the Boolean function or in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G08 is available in a variety of packages, including the ultra-small DPW package with a body size of 0.8 mm × 0.8 mm.

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Technical documentation

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Type Title Date
* Data sheet SN74LVC1G08 Single 2-Input Positive-AND Gate datasheet (Rev. Z) 26 Mar 2019
More literature Optimizing Industrial Robot CPU Boards with Logic and Voltage Translation PDF | HTML 12 Dec 2022
More literature Optimizing WLAN and WiFi Access Point Systems With Logic and Voltage Translation PDF | HTML 03 Nov 2022
More literature Implications of Slow or Floating CMOS Inputs (Rev. E) 26 Jul 2021
More literature Applications of Logic and Translation in IP Cameras (Rev. A) PDF | HTML 29 Mar 2021
More literature Optimizing HVAC Gateway Designs W/ Common Logic & Translation Voltage Use Cases (Rev. B) PDF | HTML 29 Mar 2021
More literature Simplifying Solid-State Relay Designs With Logic PDF | HTML 08 Jan 2021
More literature Enable and Disable Digital Signals PDF | HTML 04 Nov 2020
More literature Combine Power Good Signals PDF | HTML 02 Oct 2020
Selection guide Little Logic Guide 2018 (Rev. G) 06 Jul 2018
More literature Designing and Manufacturing with TI's X2SON Packages 23 Aug 2017
Selection guide Logic Guide (Rev. AB) 12 Jun 2017
More literature How to Select Little Logic (Rev. A) 26 Jul 2016
More literature Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
More literature Design Summary for WCSP Little Logic (Rev. B) 04 Nov 2004
More literature Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
More literature Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
User guide Signal Switch Data Book (Rev. A) 14 Nov 2003
More literature Use of the CMOS Unbuffered Inverter in Oscillator Circuits 06 Nov 2003
User guide LVC and LV Low-Voltage CMOS Logic Data Book (Rev. B) 18 Dec 2002
More literature Texas Instruments Little Logic Application Report 01 Nov 2002
More literature TI IBIS File Creation, Validation, and Distribution Processes 29 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
More literature 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
More literature Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 10 May 2002
More literature STANDARD LINEAR AND LOGIC FOR DVD/VCD PLAYERS 27 Mar 2002
More literature Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices 01 Dec 1997
More literature Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 01 Aug 1997
More literature CMOS Power Consumption and CPD Calculation (Rev. B) 01 Jun 1997
More literature LVC Characterization Information 01 Dec 1996
More literature Input and Output Characteristics of Digital Integrated Circuits 01 Oct 1996
More literature Live Insertion 01 Oct 1996
Design guide Low-Voltage Logic (LVC) Designer's Guide 01 Sep 1996
Application note Understanding Advanced Bus-Interface Products Design Guide 01 May 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic EVM supporting 5 through 8 pin DCK, DCT, DCU, DRL, and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
Not available on TI.com
Development kit

EVMK2GX — 66AK2Gx 1GHz evaluation module

The EVMK2GX (also known as "K2G") 1GHz evaluation module (EVM) enables developers to immediately start evaluating the 66AK2Gx processor family, and to accelerate the development of audio, industrial motor control, smart grid protection and other high reliability, real-time compute intensive (...)

User guide: PDF
Not available on TI.com
Simulation model

SN74LVC1G08 Behavioral SPICE Model

SCEM642.ZIP (7 KB) - PSpice Model
Simulation model

SN74LVC1G08 IBIS Model (Rev. A)

SCEM167A.ZIP (42 KB) - IBIS Model

Many TI reference designs include the SN74LVC1G08

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Package Pins Download
DSBGA (YZP) 5 View options
SOT-23 (DBV) 5 View options
SOT-5X3 (DRL) 5 View options
SOT-SC70 (DCK) 5 View options
USON (DRY) 6 View options
X2SON (DPW) 5 View options
X2SON (DSF) 6 View options

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