SN74AHC32Q-Q1

ACTIVE

Automotive Catalog Quadruple 2-Input Positive-OR Gates

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Automotive Catalog Quadruple 2-Input Positive-OR Gates

SN74AHC32Q-Q1

ACTIVE

Product details

Parameters

Technology Family AHC VCC (Min) (V) 2 VCC (Max) (V) 5.5 Channels (#) 4 Inputs per channel 2 IOL (Max) (mA) 8 IOH (Max) (mA) -8 Input type Standard CMOS Output type Push-Pull Features Over-Voltage Tolerant Inputs, Very High Speed (tpd 5-10ns) Data rate (Max) (Mbps) 110 Rating Automotive Operating temperature range (C) -40 to 125 open-in-new Find other OR gate

Package | Pins | Size

SOIC (D) 14 52 mm² 8.65 x 6 TSSOP (PW) 14 32 mm² 5 x 6.4 open-in-new Find other OR gate

Features

  • Qualified for Automotive Applications
  • EPIC™ (Enhanced-Performance Implanted CMOS) Process
  • Operating Range 2-V to 5.5-V VCC
  • Latch-Up Performance Exceeds 250 mA Per JESD 17
  • ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)

EPIC is a trademark of Texas Instruments.

open-in-new Find other OR gate

Description

The SN74AHC32Q is a quadruple 2-input positive-OR gate. This device performs the Boolean function
Y = A\ • B\ or Y = A + B in positive logic.

open-in-new Find other OR gate
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Technical documentation

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Type Title Date
* Datasheet Quadruple 2-Input Positive-OR Gate datasheet (Rev. A) Apr. 29, 2008
Technical articles How to keep your motor running safely Jun. 04, 2020
Selection guides Little Logic Guide 2018 (Rev. G) Jul. 06, 2018
Selection guides Logic Guide (Rev. AB) Jun. 12, 2017
Application notes How to Select Little Logic (Rev. A) Jul. 26, 2016
Application notes Implications of Slow or Floating CMOS Inputs (Rev. D) Jun. 23, 2016
Application notes Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) Dec. 02, 2015
More literature Automotive Logic Devices Brochure Aug. 27, 2014
User guides LOGIC Pocket Data Book (Rev. B) Jan. 16, 2007
More literature Design Summary for WCSP Little Logic (Rev. B) Nov. 04, 2004
Application notes Semiconductor Packing Material Electrostatic Discharge (ESD) Protection Jul. 08, 2004
Application notes Selecting the Right Level Translation Solution (Rev. A) Jun. 22, 2004
More literature Logic Cross-Reference (Rev. A) Oct. 07, 2003
Application notes Advanced High-Speed CMOS (AHC) Logic Family (Rev. C) Dec. 02, 2002
Application notes Texas Instruments Little Logic Application Report Nov. 01, 2002
Application notes TI IBIS File Creation, Validation, and Distribution Processes Aug. 29, 2002
User guides AHC/AHCT Designer's Guide February 2000 (Rev. D) Feb. 24, 2000
Application notes Benefits & Issues of Migrating 5-V and 3.3-V Logic to Lower-Voltage Supplies (Rev. A) Sep. 08, 1999
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) Apr. 01, 1998
More literature Military Advanced High-Speed CMOS Logic (AHC/AHCT) (Rev. C) Apr. 01, 1998
Application notes Migration From 3.3-V To 2.5-V Power Supplies For Logic Devices Dec. 01, 1997
Application notes Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) Aug. 01, 1997
Application notes CMOS Power Consumption and CPD Calculation (Rev. B) Jun. 01, 1997
Application notes Live Insertion Oct. 01, 1996

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARDS Download
document-generic User guide
$10.00
Description
This EVM is designed to support any logic device that has a D, DW, DB, NS, PW, P, N, or DGV package in a 14 to 24 pin count.
Features
  • Board design allows for versatility in evaluation
  • Supports a wide-range of logic devices

CAD/CAE symbols

Package Pins Download
SOIC (D) 14 View options
TSSOP (PW) 14 View options

Ordering & quality

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