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SN74AVC16T245

ACTIVE

16-Bit Dual-Supply Bus Transceiver with Configurable Voltage-Level Shifting and 3-State Outputs

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Data sheet

SN74AVC16T245

ACTIVE
Data sheet Order now

Product details

Bits (#) 16 Data rate (max) (Mbps) 380 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications RGMII Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Technology family AVC Supply current (max) (mA) 0.045 Rating Catalog Operating temperature range (°C) -40 to 85
Bits (#) 16 Data rate (max) (Mbps) 380 Topology Push-Pull Direction control (typ) Direction-controlled Vin (min) (V) 1.2 Vin (max) (V) 3.6 Vout (min) (V) 1.2 Vout (max) (V) 3.6 Applications RGMII Features Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Technology family AVC Supply current (max) (mA) 0.045 Rating Catalog Operating temperature range (°C) -40 to 85
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2V to 3.6V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • I/Os Are 4.6V Tolerant
  • Maximum Data Rates
    • 380Mbps (1.8V to 3.3V Level-Shifting)
    • 200Mbps (<1.8V to 3.3V Level-Shifting)
    • 200Mbps (Level-Shifting to 2.5V or 1.8V)
    • 150Mbps (Level-Shifting to 1.5V)
    • 100Mbps (Level-Shifting to 1.2V)
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)
  • Control Inputs VIH/VIL Levels Are Referenced to VCCA Voltage
  • VCC Isolation Feature – If Either VCC Input Is at GND, Both Ports Are in the High-Impedance State
  • Overvoltage-Tolerant Inputs and Outputs Allow Mixed-Voltage-Mode Data Communications
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate Over the Full 1.2V to 3.6V Power-Supply Range
  • Ioff Supports Partial-Power-Down Mode Operation
  • I/Os Are 4.6V Tolerant
  • Maximum Data Rates
    • 380Mbps (1.8V to 3.3V Level-Shifting)
    • 200Mbps (<1.8V to 3.3V Level-Shifting)
    • 200Mbps (Level-Shifting to 2.5V or 1.8V)
    • 150Mbps (Level-Shifting to 1.5V)
    • 100Mbps (Level-Shifting to 1.2V)
  • Latch-Up Performance Exceeds 100mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 8000V Human-Body Model (A114-A)
    • 200V Machine Model (A115-A)
    • 1000V Charged-Device Model (C101)

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC16T245 device is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. The device is operational with VCCA/VCCB as low as 1.2V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC16T245 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can be used to disable the outputs so the buses effectively are isolated.

The SN74AVC16T245 control pins (1DIR, 2DIR, 1 OE, and 2 OE) are supplied by VCCA.

This 16-bit noninverting bus transceiver uses two separate configurable power-supply rails. The SN74AVC16T245 device is optimized to operate with VCCA/VCCB set at 1.4V to 3.6V. The device is operational with VCCA/VCCB as low as 1.2V. The A port is designed to track VCCA. VCCA accepts any supply voltage from 1.2V to 3.6V. The B port is designed to track VCCB. VCCB accepts any supply voltage from 1.2V to 3.6V. This allows for universal low-voltage bidirectional translation between any of the 1.2V, 1.5V, 1.8V, 2.5V, and 3.3V voltage nodes.

The SN74AVC16T245 device is designed for asynchronous communication between data buses. The device transmits data from the A bus to the B bus or from the B bus to the A bus, depending on the logic level at the direction-control (DIR) input. The output-enable ( OE) input can be used to disable the outputs so the buses effectively are isolated.

The SN74AVC16T245 control pins (1DIR, 2DIR, 1 OE, and 2 OE) are supplied by VCCA.
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Technical documentation

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* Data sheet SN74AVC16T245 16-Bit Dual-Supply Bus Transceiver with Configurable Level-Shifting / Voltage Translation and Tri-State Outputs datasheet (Rev. F) PDF | HTML 01 Mar 2024
Selection guide Logic Guide (Rev. AC) PDF | HTML 13 Nov 2025
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 02 Oct 2024
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 12 Jul 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 03 Jul 2024
Selection guide Voltage Translation Buying Guide (Rev. A) 15 Apr 2021
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 02 Dec 2015
Application note Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B) 30 Apr 2015
User guide LOGIC Pocket Data Book (Rev. B) 16 Jan 2007
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 08 Jul 2004
Application note Selecting the Right Level Translation Solution (Rev. A) 22 Jun 2004
More literature LCD Module Interface Application Clip 09 May 2003
User guide AVC Advanced Very-Low-Voltage CMOS Logic Data Book, March 2000 (Rev. C) 20 Aug 2002
More literature Standard Linear & Logic for PCs, Servers & Motherboards 13 Jun 2002
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 22 May 2002
Application note Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B) 07 Jul 1999
Application note AVC Logic Family Technology and Applications (Rev. A) 26 Aug 1998

Design & development

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Simulation model

HSPICE Model of SN74AVC16T245

SCEJ169.ZIP (100 KB) - HSpice Model
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Simulation model

SN74AVC16T245 IBIS Model

SCEM451.ZIP (69 KB) - IBIS Model
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TSSOP (DGG) 48 Ultra Librarian
TVSOP (DGV) 48 Ultra Librarian
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