SN74LVC1G32-Q1

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Product details

Technology family LVC Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 1 Inputs per channel 2 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Standard CMOS Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Automotive Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 5 8.12 mm² (2.9 mm × 2.8 mm) USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm) SOT-SC70 (DCK) 5 4.2 mm² (2 mm × 2.1 mm)
  • Available in the small 1.45mm2 package (DRY) with 0.5mm pitch
  • Supports VCC operation: 5V
  • Inputs accept voltages to: 5.5V
  • Supports down translation to VCC
  • Maximum tpd of 3.6ns at 3.3V
  • Low power consumption: 10µA maximum ICC
  • ±24mA output drive at 3.3V
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100mA per JESD 78, Class II
  • Available in the small 1.45mm2 package (DRY) with 0.5mm pitch
  • Supports VCC operation: 5V
  • Inputs accept voltages to: 5.5V
  • Supports down translation to VCC
  • Maximum tpd of 3.6ns at 3.3V
  • Low power consumption: 10µA maximum ICC
  • ±24mA output drive at 3.3V
  • Ioff supports live insertion, partial-power-down mode, and back-drive protection
  • Latch-up performance exceeds 100mA per JESD 78, Class II

This single 2-input positive-OR gate is designed for 1.65V to 5.5V VCC operation.

The SN74LVC1G32-Q1 device performs the Boolean function Y = A + B or Y = Ā · B in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G32-Q1 device is available in a variety of packages, including the small DRY package with a body size of 1.45 × 1.00mm.

This single 2-input positive-OR gate is designed for 1.65V to 5.5V VCC operation.

The SN74LVC1G32-Q1 device performs the Boolean function Y = A + B or Y = Ā · B in positive logic.

The CMOS device has high output drive while maintaining low static power dissipation over a broad VCC operating range.

The SN74LVC1G32-Q1 device is available in a variety of packages, including the small DRY package with a body size of 1.45 × 1.00mm.

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Technical documentation

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Top documentation Type Title Format options Date
Application brief User Fewer Inputs to Monitor Error Signals PDF | HTML Jul 16, 2021
More literature Automotive Logic Devices Brochure Aug 27, 2014

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

5-8-LOGIC-EVM — Generic logic evaluation module for 5-pin to 8-pin DCK, DCT, DCU, DRL and DBV packages

Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
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Evaluation board

5-8-NL-LOGIC-EVM — Generic logic and translation EVM supporting 5 to 8 pin DPW, DQE, DRY, DSF, DTM, DTQ and DTT pkgs

Generic EVM designed to support any logic or translation device that has a DTT, DRY, DPW, DTM, DQE, DQM, DSF, or DTQ package. Board design allows for flexible evaluation.

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Simulation model

HSPICE Model for SN74LVC1G32

SCEJ254.ZIP (87 KB) - HSpice model
Supported products & hardware
Simulation model

SN74LVC1G32 Behavioral SPICE Model

SCEM632.ZIP (7 KB) - PSpice model
Supported products & hardware
Simulation model

SN74LVC1G32 IBIS Model (Rev. C)

SCEM168C.ZIP (43 KB) - IBIS model
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Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOT-23 (DBV) 5 Ultra Librarian
USON (DRY) 6 Ultra Librarian
SOT-SC70 (DCK) 5 Ultra Librarian

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