SN74LVC2G34 Dual Buffer Gate | TI.com

SN74LVC2G34
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Dual Buffer Gate

Dual Buffer Gate - SN74LVC2G34
Datasheet
 

Description

The SN74LVC2G34 device is a dual buffer gate designed for 1.65-V to 5.5-V VCC operation. The SN74LVC2G34 device performs the Boolean function Y = A in positive logic.

NanoFree package technology is a major breakthrough in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

Features

  • Available in the Texas Instruments NanoFree Package
  • Supports 5.5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Maximum tpd of 4.1 ns at 3.3 V
  • Low Power Consumption, 10-µA Maximum ICC
  • ±24-mA Output Drive at 3.3 V
  • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
  • Typical VOHV (Output VOH Undershoot) >2 V at VCC = 3.3 V, TA = 25°C
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Can Be Used as a Down Translator to Translate Inputs From a Maximum of 5.5 V Down to the VCC Level
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)

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Parametrics

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Part number Order Technology Family VCC (Min) (V) VCC (Max) (V) Channels (#) IOL (Max) (mA) IOH (Max) (mA) ICC (uA) Input type Output type Features Data rate (Mbps) Rating Operating temperature range (C) Package Group
SN74LVC2G34 Order now LVC     1.65     5.5     2     32     -32     10     Standard CMOS     Push-Pull     Balanced outputs
Very high speed (tpd 5-10ns)
Partial power down (Ioff)
Over-voltage tolerant inputs    
300     Catalog     -40 to 125
-40 to 85    
DSBGA | 6
SC70 | 6
SOT-23 | 6
SOT-5X3 | 6