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SN74LVCZ161284A

ACTIVE

19-Bit IEEE 1284 Std Bus Interface

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Data sheet

SN74LVCZ161284A

ACTIVE
Data sheet Order now

Product details

Bits (#) 19 Data rate (max) (Mbps) 150 Topology Open drain Vin (min) (V) 3 Vin (max) (V) 5.5 Vout (min) (V) 3 Vout (max) (V) 3.6 Applications IEEE1284 Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 22 Technology family LVC Supply current (max) (mA) 45 Rating Catalog Operating temperature range (°C) 0 to 70
Bits (#) 19 Data rate (max) (Mbps) 150 Topology Open drain Vin (min) (V) 3 Vin (max) (V) 5.5 Vout (min) (V) 3 Vout (max) (V) 3.6 Applications IEEE1284 Features Output damping resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff) Prop delay (ns) 22 Technology family LVC Supply current (max) (mA) 45 Rating Catalog Operating temperature range (°C) 0 to 70
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm)
  • Power-On Reset (POR) Prevents Printer Errors When Printer Is Turned On, But No Valid Signal Is at Pins A9–A13
  • Operates From 3 V to 3.6 V
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • Designed for the IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 350-V Machine Model (A115-A)
    • 1500-V Charged-Device Model (C101)
  • Power-On Reset (POR) Prevents Printer Errors When Printer Is Turned On, But No Valid Signal Is at Pins A9–A13
  • Operates From 3 V to 3.6 V
  • 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
  • Designed for the IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
  • Flow-Through Architecture Optimizes PCB Layout
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model (A114-A)
    • 350-V Machine Model (A115-A)
    • 1500-V Charged-Device Model (C101)

The SN74LVCZ161284A is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high, and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side, and four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The Power-On Reset (POR) ensures that the Y outputs (Y9–Y13) stay in the high state after power on until an associated input (A9–A13) goes high. When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer system errors caused by deasserting the BUSY signal in the cable at power on.

The SN74LVCZ161284A is designed for 3-V to 3.6-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.

This device has eight bidirectional bits; data can flow in the A-to-B direction when the direction-control input (DIR) is high, and in the B-to-A direction when DIR is low. This device also has five drivers that drive the cable side, and four receivers. The SN74LVCZ161284A has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.

The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and peripheral logic out (PERI LOGIC OUT), all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.

The device has two supply voltages. VCC is designed for 3-V to 3.6-V operation. VCC CABLE supplies the inputs and output buffers of the cable side only and is designed for 3-V to 3.6-V and for 4.7-V to 5.5-V operation. Even when VCC CABLE is 3 V to 3.6 V, the cable-side I/O pins are 5-V tolerant.

The Power-On Reset (POR) ensures that the Y outputs (Y9–Y13) stay in the high state after power on until an associated input (A9–A13) goes high. When an associated input goes high, all Y outputs are activated, and noninverting signals of the associated inputs are driven through Y outputs. This special feature prevents printer system errors caused by deasserting the BUSY signal in the cable at power on.
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Technical documentation

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* Data sheet SN74LVCZ161284A,19-Bit IEEE1284 Translation Transceiver With Error-Free Power-Up datasheet (Rev. B) Sep 16, 2002
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML Jul 12, 2024
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML Jul 3, 2024
Selection guide Voltage Translation Buying Guide (Rev. A) Apr 15, 2021

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