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The TRF371125 is a highly linear and integrated direct-conversion quadrature demodulator. The TRF371125 integrates balanced I and Q mixers, LO buffers, and phase splitters to convert an RF signal directly to I and Q baseband. The on-chip programmable-gain amplifiers allow adjustment of the output signal level without the need for external variable-gain (attenuator) devices. The TRF371125 integrates programmable baseband low-pass filters that attenuate nearby interference, eliminating the need for an external baseband filter.
Housed in a 7-mm × 7-mm QFN package, the TRF371125 provides the smallest and most integrated receiver solution available for high-performance equipment.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | TRF371125 Integrated IQ Demodulator datasheet (Rev. B) | Dec 3, 2010 | |
| Technical article | Can a clock generator act as a jitter cleaner? | PDF | HTML | Mar 23, 2017 | |
| Technical article | Don’t let bad reference signals destroy the phase noise in your PLL/synthesizer | PDF | HTML | Jan 10, 2017 | |
| Technical article | A survival guide to scaling your PLL loop filter design | PDF | HTML | Nov 22, 2016 | |
| User guide | TSW6011EVM Quick Start Guide (Rev. D) | Aug 17, 2016 | ||
| Technical article | What to do when your PLL does not lock | PDF | HTML | Jul 12, 2016 | |
| Technical article | Issues with jitter, phase noise, lock time or spurs? Check the loop-filter bandwid | PDF | HTML | Jun 6, 2016 | |
| Application note | Characterization Report for FMC30RF | Sep 18, 2014 | ||
| Application note | DC Offset Auto-Calibration of TRF371x | Nov 5, 2009 |
For additional terms or required resources, click any title below to view the detail page where available.
The TRF371125EVM is the evaluation module for the TRF371125 device. The TRF371125 is a direct conversion quadrature demodulator which integrates programmable baseband filters, adjustable DC offset correction, and output buffer amplifiers for driving high speed ADCs. The TRF371125 is suited for (...)
The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RGZ) | 48 | Ultra Librarian |
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