Direct Down-Conversion System with I/Q Correction


Design files


The I/Q Correction block implemented in the Field Programmable Gate Array (FPGA) of the TSW6011EVM helps users to adopt a direct down conversion receiver architecture in a wireless system. The I/Q correction block consists of a single-tap blind algorithm, which corrects the frequency-independent I/Q imbalance in a complex zero-IF receiver system. Along with the I/Q correction block, the FPGA includes a digital gain block, a digital power-measurement block, x2 of interpolation block, an I/Q offset correction block, and a quadrature mixing block.

  1. Direct Down conversion receiver signal chain with automatic IQ correction
  2. Includes TRF371125 IQ demod for direct conversion to baseband
  3. ADS5282 to capture the IQ receive signal for IQ processing
  4. Automatic blind IQ correction IP example provided on Altera Cyclone III FPGA
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.

SLWU085.PDF (2311 K)

Reference design overview and verified performance test data

SLWR040.PDF (349 K)

Detailed schematic diagram for design layout and components

TIDR727.PDF (68 K)

Complete listing of design components, reference designators, and manufacturers/part numbers

TIDR728.ZIP (2213 K)

Detailed overview of design layout for component placement


Includes TI products in the design and potential alternatives.

IQ demodulators

TRF3711250.7 - 4.0 GHz Wide Bandwidth Integrated Direct Down Conversion Receiver

Data sheet: PDF
Buck converters (integrated switch)

TPS546103V to 6V Input, 6A Synchronous Step-Down Converter

Data sheet: PDF | HTML
Clock generators

CDCE620055/10 outputs clock generator/jitter cleaner with integrated dual VCO

Data sheet: PDF | HTML
High-speed ADCs (≥10 MSPS)

ADS5282Eight-Channel, 12-Bit, 65-MSPS Analog-to-Digital Converter (ADC)

Data sheet: PDF
High-speed DACs (>10 MSPS)

DAC5672Dual-Channel, 14-Bit, 275-MSPS Digital-to-Analog Converter (DAC)

Data sheet: PDF
Linear & low-dropout (LDO) regulators

TPS76050-mA, 16-V, low-dropout voltage regulator with enable

Data sheet: PDF
Linear & low-dropout (LDO) regulators

TPS7671-A, 10-V, low-dropout voltage regulator with enable & RESET with delay

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
Design guide Direct Down-Conversion System With I/Q Correction (TIDA-00078 CerTIfied Design) Jul. 23, 2013

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