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UCC21541

ACTIVE

Reinforced, 1.5A/2.5A dual-channel isolated gate driver w/ disable, programmable deadtime

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Data sheet

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UCC21550 ACTIVE Reinforced, 4A/6A dual-channel isolated gate driver w/ disable, programmable deadtime Next gen P2P refresh

UCC21541

ACTIVE
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Product details

Number of channels 2 Isolation rating Reinforced Power switch GaNFET, IGBT, MOSFET Withstand isolation voltage (VISO) (Vrms) 5000 Working isolation voltage (VIOWM) (Vrms) 1000 Transient isolation voltage (VIOTM) (VPK) 7070 Peak output current (A) 2.5 Peak output current (source) (typ) (A) 1.5 Peak output current (sink) (typ) (A) 2.5 Features Disable, Programmable dead time Output VCC/VDD (min) (V) 9.2 Output VCC/VDD (max) (V) 18 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 1414 Rise time (ns) 8 Fall time (ns) 9 Undervoltage lockout (typ) (V) 8
Number of channels 2 Isolation rating Reinforced Power switch GaNFET, IGBT, MOSFET Withstand isolation voltage (VISO) (Vrms) 5000 Working isolation voltage (VIOWM) (Vrms) 1000 Transient isolation voltage (VIOTM) (VPK) 7070 Peak output current (A) 2.5 Peak output current (source) (typ) (A) 1.5 Peak output current (sink) (typ) (A) 2.5 Features Disable, Programmable dead time Output VCC/VDD (min) (V) 9.2 Output VCC/VDD (max) (V) 18 Input supply voltage (min) (V) 3 Input supply voltage (max) (V) 5.5 Propagation delay time (µs) 0.028 Input threshold CMOS, TTL Operating temperature range (°C) -40 to 125 Rating Catalog Bootstrap supply voltage (max) (V) 1414 Rise time (ns) 8 Fall time (ns) 9 Undervoltage lockout (typ) (V) 8
SOIC (DW) 16 106.09 mm² (10.3 mm × 10.3 mm)
  • Wide body package options
    • DW SOIC-16: pin-2-pin to UCC21520
    • DWK SOIC-14: 3.3 mm Ch-2-Ch spacing
  • Up to 4A peak source and 6A peak sink output
  • Up to 18V VDD output drive supply
    • 5V and 8V VDD UVLO options
  • CMTI greater than 125V/ns
  • Switching parameters:
    • 33ns typical propagation delay
    • 6ns maximum pulse-width distortion
    • 10µs maximum VDD power-up delay
  • Resistor-programmable dead time
  • TTL and CMOS compatible inputs
  • Safety-related certifications (planned):
    • 8000VPK reinforced isolation per DIN EN IEC 60747-17 (VDE 0884-17)
    • 5700VRMS isolation for 1 minute per UL 1577
    • CQC certification per GB4943.1-2022
  • Wide body package options
    • DW SOIC-16: pin-2-pin to UCC21520
    • DWK SOIC-14: 3.3 mm Ch-2-Ch spacing
  • Up to 4A peak source and 6A peak sink output
  • Up to 18V VDD output drive supply
    • 5V and 8V VDD UVLO options
  • CMTI greater than 125V/ns
  • Switching parameters:
    • 33ns typical propagation delay
    • 6ns maximum pulse-width distortion
    • 10µs maximum VDD power-up delay
  • Resistor-programmable dead time
  • TTL and CMOS compatible inputs
  • Safety-related certifications (planned):
    • 8000VPK reinforced isolation per DIN EN IEC 60747-17 (VDE 0884-17)
    • 5700VRMS isolation for 1 minute per UL 1577
    • CQC certification per GB4943.1-2022

The UCC2154x is an isolated dual channel gate driver family designed with up to 4 A/6 A peak source/sink current to drive power MOSFET, IGBT, and GaN transistors. UCC2154x in DWK package also offers 3.3-mm minimum channel-to-channel spacing, which facilitates higher bus voltage.

The UCC2154x family can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5.7-kVRMS isolation barrier, with a minimum of 125-V/ns common-mode transient immunity (CMTI).

Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, and negative voltage handling for up to –5-V spikes for 50 ns on input pins. All supplies have UVLO protection.

The UCC2154x is an isolated dual channel gate driver family designed with up to 4 A/6 A peak source/sink current to drive power MOSFET, IGBT, and GaN transistors. UCC2154x in DWK package also offers 3.3-mm minimum channel-to-channel spacing, which facilitates higher bus voltage.

The UCC2154x family can be configured as two low-side drivers, two high-side drivers, or a half-bridge driver. The input side is isolated from the two output drivers by a 5.7-kVRMS isolation barrier, with a minimum of 125-V/ns common-mode transient immunity (CMTI).

Protection features include: resistor programmable dead time, disable feature to shut down both outputs simultaneously, and negative voltage handling for up to –5-V spikes for 50 ns on input pins. All supplies have UVLO protection.
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UCC21542 ACTIVE Reinforced, 4A/6A dual-channel isolated gate driver w/ disable Non-Programmable deadtime version

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet UCC2154x Reinforced Isolation Dual-Channel Gate Driver With 3.3mm Channel-to-Channel Spacing Option datasheet (Rev. E) PDF | HTML Nov 8, 2024
Certificate UCC21540 CQC Certificate of Product Certification PDF | HTML Aug 17, 2023
Application brief The Use and Benefits of Ferrite Beads in Gate Drive Circuits PDF | HTML Dec 16, 2021
Certificate CQC19001226951 Feb 5, 2021
Test report Peak Efficiency at 99%, 585-W High-Voltage Buck Reference Design Apr 24, 2020

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

UCC21540EVM — 5.0-kVrms Isolated Dual-Channel Gate Driver With 3.3mm Channel-to-Channel Spacing Evaluation Module

UCC21540EVM is designed for evaluating UCC21540, which is an isolated dual-channel gate driver with 4-A source and 6-A sink peak current capability. This EVM serves as a reference design for driving power MOSFETs with up to 18V drive voltage, UCC21540 pin function identification, components (...)
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Simulation model

UCC21541 PSpice Transient Model

SLUM657.ZIP (20 KB) - PSpice model
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Reference design

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Reference design

TIDA-010210 — 11-kW, bidirectional, three-phase ANPC based on GaN reference design

This reference design provides a design template for implementing a three-level, three-phase, gallium nitride (GaN) based ANPC inverter power stage. The use of fast switching power devices makes it possible to switch at a higher frequency of 100 kHz, reducing the size of magnetics for the filter (...)

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