Inicio Convertidores de datos Convertidores analógico-digitales (ADC) ADC de alta velocidad (≥ 10 MSPS)
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Convertidores de datos
Convertidores analógico-digitales (ADC)
ADC de alta velocidad (≥ 10 MSPS)

ADC12DJ800-Q1

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Convertidor analógico a digital (ADC) de dos canales, 12 bits y 800 MSPS para automoción con interfa

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ADC12DJ800-Q1

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Detalles del producto

Sample rate (max) (Msps) 800 Resolution (Bits) 12 Number of input channels 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Automotive Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1110 Architecture Folding Interpolating SNR (dB) 57.6 ENOB (bit) 9 SFDR (dB) 62 Operating temperature range (°C) -40 to 125 Input buffer Yes
Sample rate (max) (Msps) 800 Resolution (Bits) 12 Number of input channels 2 Interface type JESD204B, JESD204C Analog input BW (MHz) 6000 Features Ultra High Speed Rating Automotive Peak-to-peak input voltage range (V) 0.8 Power consumption (typ) (mW) 1110 Architecture Folding Interpolating SNR (dB) 57.6 ENOB (bit) 9 SFDR (dB) 62 Operating temperature range (°C) -40 to 125 Input buffer Yes
FCCSP (AAV) 144 100 mm² 10 x 10
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 800 MSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (97 MHz): 57.6 dBFS
    • ENOB (97 MHz): 9.0 Bits
    • SFDR (97 MHz): 62 dBFS
    • Noise floor (–20 dBFS): –146.1 dBFS/Hz
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800 MSPS):
    • Quad Channel: 415 mW / channel
    • Dual channel: 555 mW / channel
    • Single channel: 830 mW
  • Power supplies: 1.1 V, 1.9 V
  • AEC-Q100 qualified for automotive applications:
    • Temperature grade 1: –40°C to +125°C, TA
  • ADC Core:
    • Resolution: 12 Bit
    • Maximum sampling rate: 800 MSPS
    • Non-interleaved architecture
    • Internal dither reduces high-order harmonics
  • Performance specifications (–1 dBFS):
    • SNR (97 MHz): 57.6 dBFS
    • ENOB (97 MHz): 9.0 Bits
    • SFDR (97 MHz): 62 dBFS
    • Noise floor (–20 dBFS): –146.1 dBFS/Hz
  • Full-scale input voltage: 800 mVPP-DIFF
  • Full-power input bandwidth: 6 GHz
  • JESD204C Serial data interface:
    • Support for 2 to 8 (Quad/Dual channel) or 1 to 4 (Single channel) total SerDes lanes
    • Maximum baud-rate: 17.16 Gbps
    • 64B/66B and 8B/10B encoding modes
    • Subclass-1 support for deterministic latency
    • Compatible with JESD204B receivers
  • Optional internal sampling clock generation
    • Internal PLL and VCO (7.2–8.2 GHz)
  • SYSREF Windowing eases synchronization
  • Four clock outputs simplify system clocking
    • Reference clocks for FPGA or adjacent ADC
    • Reference clock for SerDes transceivers
  • Timestamp input and output for pulsed systems
  • Power consumption (800 MSPS):
    • Quad Channel: 415 mW / channel
    • Dual channel: 555 mW / channel
    • Single channel: 830 mW
  • Power supplies: 1.1 V, 1.9 V

ADC12xJ800-Q1 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC12xJ800-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3 dB) of 6 GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band.

ADC12xJ800-Q1 is a family of quad, dual and single channel, 12-bit, 800 MSPS analog-to-digital converters (ADC). Low power consumption, high sampling rate and 12-bit resolution makes the ADC12xJ800-Q1 suited for light detection and ranging (LiDAR) systems. The ADC12xJ800-Q1 is qualified for automotive applications.

Full-power input bandwidth (-3 dB) of 6 GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of of L-band and S-band.
open-in-new Buscar otro/a ADC de alta velocidad (≥ 10 MSPS)
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* Data sheet ADC12xJ800-Q1 Quad, Dual, Single Channel, 800-MSPS, 12-bit, Analog-to-Digital Converter (ADC) with JESD204C Interface datasheet PDF | HTML 22 abr 2020

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PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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FCCSP (AAV) 144 Ver opciones
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