SN74LV126A

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Búferes de 4 canales, de 2 V a 5.5 V con salidas de 3 estados

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Hoja de datos

document-pdfAcrobat SN74LV126A Quadruple Bus Buffer Gates With 3-State Outputs datasheet (Rev. J) (Inglés) PDF | HTML

SN74LV126A

ACTIVO

Hoja de datos

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Detalles del producto

Technology family

LV-A

Number of channels

4

IOL (max) (mA)

16

Supply current (max) (µA)

20

IOH (max) (mA)

-16

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

Technology family

LV-A

Number of channels

4

IOL (max) (mA)

16

Supply current (max) (µA)

20

IOH (max) (mA)

-16

Input type

Standard CMOS

Output type

3-State

Features

Balanced outputs, Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns)

Rating

Catalog

Operating temperature range (°C)

-40 to 125

SOIC (D)

14

51.9 mm² (8.65 mm × 6 mm)

TVSOP (DGV)

14

23.04 mm² (3.6 mm × 6.4 mm)

SOP (NS)

14

79.56 mm² (10.2 mm × 7.8 mm)

TSSOP (PW)

14

32 mm² (5 mm × 6.4 mm)

SSOP (DB)

14

48.36 mm² (6.2 mm × 7.8 mm)

2V to 5.5V VCC operation
Maximum tpd of 6.5ns at 5V
Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
Ioff supports live insertion, partial power down mode, and back drive protection
Support mixed-mode voltage operation on all ports
Latch-up performance exceeds 250mAper JESD 17

2V to 5.5V VCC operation
Maximum tpd of 6.5ns at 5V
Typical VOLP (output ground bounce) <0.8V at VCC = 3.3V, TA = 25°C
Typical VOHV (output VOH undershoot) >2.3V at VCC = 3.3V, TA = 25°C
Ioff supports live insertion, partial power down mode, and back drive protection
Support mixed-mode voltage operation on all ports
Latch-up performance exceeds 250mAper JESD 17

The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

The SN74LV126A quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

These quadruple bus buffer gates are designed for 2V to 5.5V VCC operation.

The SN74LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

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Documentación principal	Tipo	Título	Opciones de formato	Descargar la versión más reciente en inglés	Fecha
*	Hoja de datos	SN74LV126A Quadruple Bus Buffer Gates With 3-State Outputs datasheet (Rev. J)	PDF \| HTML		4/04/2024

Diseño y desarrollo

Para conocer los términos adicionales o los recursos necesarios, haga clic en cualquier título de abajo para ver la página de detalles cuando esté disponible.

Placa de evaluación

14-24-LOGIC-EVM — Módulo de evaluación genérico de productos lógicos para encapsulados D, DB, DGV, DW, DYY, NS y PW de

El módulo de evaluación (EVM) 14-24-LOGIC-EVM está diseñado para admitir cualquier dispositivo lógico que se encuentre en un encapsulado D, DW, DB, NS, PW, DYY o DGV de 14 a 24 pines.

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