625-pin (CZH) package image

TMS320C6654CZH8 활성

고성능 싱글 코어 C66x 고정 및 부동 소수점 DSP - 최고 850MHz

가격

수량 가격
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품질 정보

등급 Catalog
RoHS
REACH
MSL 등급/피크 리플로우 Level-3-245C-168 HR
품질, 신뢰성
및 패키징 정보

포함된 정보:

  • RoHS
  • REACH
  • 디바이스 마킹
  • 납 마감/볼 재질
  • MSL 등급/피크 리플로우
  • MTBF/FIT 예측
  • 물질 성분
  • 인증 요약
  • 지속적인 신뢰성 모니터링
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추가 제조 정보

포함된 정보:

  • 팹 위치
  • 조립 위치
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수출 분류

*참조 목적

  • US ECCN: 3A991A1

패키징 정보

패키지 | 핀 FCBGA (CZH) | 625
작동 온도 범위(°C) 0 to 85
패키지 수량 | 캐리어 60 | JEDEC TRAY (5+1)

TMS320C6654의 주요 특징

  • One TMS320C66x DSP Core Subsystem (CorePac)
    • C66x Fixed- and Floating-Point CPU Core: Up to 850 MHz for C6654 and 600 MHz for C6652
  • Multicore Shared Memory Controller (MSMC)
    • Memory Protection Unit for DDR3_EMIF
  • Multicore Navigator
    • 8192 Multipurpose Hardware Queues with Queue Manager
    • Packet-Based DMA for Zero-Overhead Transfers
  • Peripherals
    • PCIe Gen2 (C6654 Only)
      • Single Port Supporting 1 or 2 Lanes
      • Supports up to 5 GBaud Per Lane
    • Gigabit Ethernet (GbE) Subsystem (C6654 Only)
      • One SGMII Port (C6654 Only)
      • Supports 10-, 100-, and 1000-Mbps Operation
    • 32-Bit DDR3 Interface
      • DDR3-1066
      • 4GB of Addressable Memory Space
    • 16-Bit EMIF
    • Universal Parallel Port
      • Two Channels of 8 Bits or 16 Bits Each
      • Supports SDR and DDR Transfers
    • Two UART Interfaces
    • Two Multichannel Buffered Serial Ports (McBSPs)
    • I2C Interface
    • 32 GPIO Pins
    • SPI Interface
    • Semaphore Module
    • Eight 64-Bit Timers
    • Two On-Chip PLLs
  • Commercial Temperature:
    • 0°C to 85°C
  • Extended Temperature:
    • –40°C to 100°C

TMS320C6654에 대한 설명

The C6654 and C6652 are high performance fixed- and floating-point DSPs that are based on TI’s KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can run at a core speed of up to 850 MHz for C6654 and 600 MHz for C6652. For developers of a broad range of applications, both C6654 and C6652 DSPs enable a platform that is power-efficient and easy to use. In addition, the C6654 and C6652 DSPs are fully backward compatible with all existing C6000™ family of fixed- and floating-point DSPs.

TI’s KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores, memory subsystem, peripherals, and accelerators) and uses several innovative components and techniques to maximize intradevice and interdevice communication that lets the various DSP resources operate efficiently and seamlessly. Central to this architecture are key components such as Multicore Navigator that allows for efficient data management between the various device components. The TeraNet is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore shared memory controller allows access to shared and external memory directly without drawing from switch fabric capacity.

For fixed-point use, the C66x core has 4× the multiply accumulate (MAC) capability of C64x+ cores. In addition, the C66x core integrates floating-point capability and the per-core raw computational performance is an industry-leading 27.2 GMACS per core and 13.6 GFLOPS per core (@850 MHz frequency). The C66x core can execute 8 single precision floating-point MAC operations per cycle and can perform double- and mixed-precision operations and is IEEE 754 compliant. The C66x core incorporates 90 new instructions (compared to the C64x+ core) targeted for floating-point and vector math oriented processing. These enhancements yield sizeable performance improvements in popular DSP kernels used in signal processing, mathematical, and image acquisition functions. The C66x core is backward code-compatible with TI’s previous generation C6000 fixed- and floating-point DSP cores, ensuring software portability and shortened software development cycles for applications migrating to faster hardware.

The C6654 and C6652 DSPs integrate a large amount of on-chip memory. In addition to 32KB of L1 program and data cache, 1024KB of dedicated memory can be configured as mapped RAM or cache. All L2 memories incorporate error detection and error correction. For fast access to external memory, this device includes a 32-bit DDR-3 external memory interface (EMIF) running at a rate of 1066 MHz and has ECC DRAM support.

This family supports a number of high-speed standard interfaces including PCI Express Gen2 and Gigabit Ethernet (PCIe and Gigabit Ethernet are not supported on the C6652). This family of DSPs also includes I2C, UART, Multichannel Buffered Serial Port (McBSP), Universal Parallel Port (uPP), and a 16-bit asynchronous EMIF, along with general-purpose CMOS IO.

The C6654 and C6652 devices have a complete set of development tools, which includes: an enhanced C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows® debugger interface for visibility into source code execution.

TI’s KeyStone Multicore Architecture provides a high performance structure for integrating RISC and DSP cores with application-specific coprocessors and I/O. The KeyStone architecture is the first of its kind that provides adequate internal bandwidth for nonblocking access to all processing cores, peripherals, coprocessors, and I/O. This internal bandwidth is achieved with four main hardware elements: Multicore Navigator, TeraNet, and Multicore Shared Memory Controller.

Multicore Navigator is an innovative packet-based manager that controls 8192 queues. When tasks are allocated to the queues, Multicore Navigator provides hardware-accelerated dispatch that directs tasks to the appropriate available hardware. The packet-based system on a chip (SoC) uses the two Tbps capacity of the TeraNet switched central resource to move packets. The Multicore Shared Memory Controller lets processing cores access shared memory directly without drawing from the capacity of TeraNet, so packet movement cannot be blocked by memory access.

가격

수량 가격
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캐리어 옵션

전체 릴, 맞춤형 수량의 릴, 절단 테이프, 튜브, 트레이 등 부품 수량에 따라 다양한 캐리어 옵션을 선택할 수 있습니다.

맞춤형 릴은 한 릴에서 절단 테이프의 연속 길이로, 로트 및 날짜 코드 추적 기능을 유지하여 요청한 정확한 양을 유지합니다. 업계 표준에 따라, 황동 심으로 절단 테이프 양쪽에 18인치 리더와 트레일러를 연결하여 자동화 조립 기계에 직접 공급합니다. TI는 맞춤형 수량의 릴 주문 시 릴 요금을 부과합니다.

절단 테이프란 릴에서 잘라낸 테이프 길이입니다. TI는 요청 수량을 맞추기 위해 여러 가닥의 절단 테이프 또는 박스를 사용하여 주문을 이행할 수 있습니다.

TI는 종종 재고 가용성에 따라 튜브 또는 트레이 디바이스를 박스나 튜브 또는 트레이로 배송합니다. TI는 내부 정전 방전 및 습도 민감성 수준 보호 요구 사항에 따라 모든 테이프, 튜브 또는 샘플 박스를 포장합니다.

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