패키징 정보
| 패키지 | 핀 WQFN (RUA) | 42 |
| 작동 온도 범위(°C) -40 to 85 |
| 패키지 수량 | 캐리어 3,000 | LARGE T&R |
TS3DDR3812의 주요 특징
- Compatible with DDR3 SDRAM Standard (JESD79-3D)
- Wide Bandwidth of 1.675 GHz
- Low Propagation Delay (tpd = 40 ps Typ)
- Low Bit-to-Bit Skew (tsk(o) = 6 ps Typ)
- Low and Flat ON-State Resistance
(rON = 8 Ω Typ) - Low Input/Output Capacitance
(CON = 5.6 pF Typ) - Low Crosstalk
(XTALK = –43 dB,
Typ at 250 MHz) - VCC Operating Range from 3 V to 3.6 V
- Rail-to-Rail Switching on Data I/O Ports
(0 to VCC) - Separate Switch Control Logic for Upper and Lower 6-Channels
- Dedicated Enable Logic Supports Hi-Z Mode
- IOFF Protection Prevents Current Leakage in Powered Down State (VCC = 0 V)
- ESD Performance Tested Per
JESD22
- 2000 V Human Body Model
(A114B, Class II) - 1000 V Charged Device Model (C101)
- 2000 V Human Body Model
- 42-pin RUA Package (9 × 3.5 mm, 0.5 mm Pitch)
TS3DDR3812에 대한 설명
The TS3DDR3812 is a 12-channel, 1:2 multiplexer/demultiplexer switch designed for DDR3 applications. It operates from a 3 to 3.6 V supply and offers low and flat ON-state resistance as well as low I/O capacitance which allow it to achieve a typical bandwidth of 1.675 GHz.
Channels A0 through A11 are divided into two banks of six bits and are independently controlled via two digital inputs called SEL1 and SEL2. These select inputs control the switch position of each 6-bit DDR3 source and allow them to be routed to one of two end-points. Alternatively, the switch can be used to connect a single endpoint to one of two 6-bit DDR3 sources. For switching 12-bit DDR3 sources, simply connect SEL1 and SEL2 together externally and control all 12 channels with a single GPIO input. An EN input allows the entire chip to be placed into a high-impedance (Hi-Z) state while not in use.
These characteristics make the TS3DDR3812 an excellent choice for use in memory, analog/digital video, LAN, and other high-speed signal switching applications.