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SN74LVC1G97

ACTIVE

Configurable Multiple-Function Gate

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Data sheet

SN74LVC1G97

ACTIVE
Data sheet Order now

Product details

Technology family LVC Number of channels 1 Inputs per channel 3 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
Technology family LVC Number of channels 1 Inputs per channel 3 IOL (max) (mA) 32 IOH (max) (mA) -32 Input type Schmitt-Trigger Output type Push-Pull Features Over-voltage tolerant inputs, Partial power down (Ioff), Very high speed (tpd 5-10ns) Data rate (max) (Mbps) 100 Rating Catalog Operating temperature range (°C) -40 to 125
SOT-23 (DBV) 6 8.12 mm² (2.9 mm × 2.8 mm) SOT-5X3 (DRL) 6 2.56 mm² (1.6 mm × 1.6 mm) SOT-SC70 (DCK) 6 4.2 mm² (2 mm × 2.1 mm) DSBGA (YZP) 6 2.1875 mm² (— mm × — mm) USON (DRY) 6 1.45 mm² (1.45 mm × 1 mm) X2SON (DSF) 6 1 mm² (1 mm × 1 mm)
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree&traDe; Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Max tpd of 6.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Choose From Nine Specific Logic Functions
  • ESD Protection Exceeds JESD 22
    • 2000-V Human Body Model (A114-A)
    • 200-V Machine Model (A115-A)
    • 1000-V Charged-Device Model (C101)
  • Available in the Texas Instruments NanoFree&traDe; Package
  • Supports 5-V VCC Operation
  • Inputs Accept Voltages to 5.5 V
  • Supports Down Translation to VCC
  • Max tpd of 6.3 ns at 3.3 V
  • Low Power Consumption, 10-µA Max ICC
  • ±24-mA Output Drive at 3.3 V
  • Ioff Supports Live Insertion, Partial-Power-Down Mode, and Back-Drive Protection
  • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
  • Choose From Nine Specific Logic Functions

The SN74LVC1G97 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to VCC or GND.

This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.

This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

NanoFree package technology is a major break-through in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

The SN74LVC1G97 device features configurable multiple functions. The output state is determined by eight patterns of 3-bit input. The user can choose the logic functions MUX, AND, OR, NAND, NOR, inverter, and noninverter. All inputs can be connected to VCC or GND.

This configurable multiple-function gate is designed for 1.65-V to 5.5-V VCC operation.

This device functions as an independent gate, but because of Schmitt action, it may have different input threshold levels for positive-going (VT+) and negative-going (VT–) signals.

NanoFree package technology is a major break-through in IC packaging concepts, using the die as the package.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
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SN74AUP1G97 ACTIVE Low-Power Configurable Multiple-Function Gate Voltage range 0.8V to 3.6V, average propagation delay 8ns, average drive strength 4mA

Technical documentation

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Top documentation Type Title Format options Date
* Data sheet SN74LVC1G97 Configurable Multiple-Function Gate datasheet (Rev. N) PDF | HTML Jan 4, 2017
Application brief Understanding Schmitt Triggers (Rev. B) PDF | HTML Apr 17, 2025
Application brief Utilizing Configurable Logic in System Design PDF | HTML Oct 30, 2024
More literature SN74LVC1G97 and SN74LVC1G98 Product Clip (Rev. A) Jul 13, 2004

Design & development

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Evaluation board

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Flexible EVM designed to support any device that has a DCK, DCT, DCU, DRL, or DBV package in a 5 to 8 pin count.
User guide: PDF
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Evaluation board

5-8-NL-LOGIC-EVM — Generic logic and translation EVM supporting 5 to 8 pin DPW, DQE, DRY, DSF, DTM, DTQ and DTT pkgs

Generic EVM designed to support any logic or translation device that has a DTT, DRY, DPW, DTM, DQE, DQM, DSF, or DTQ package. Board design allows for flexible evaluation.

User guide: PDF | HTML
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Simulation model

SN74LVC1G97 IBIS Model (Rev. A)

SCEM306 (241 KB) - IBIS model
Supported products & hardware
Reference design

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Supported products & hardware
Package Pins CAD symbols, footprints & 3D models
SOT-23 (DBV) 6 Ultra Librarian
SOT-5X3 (DRL) 6 Ultra Librarian
SOT-SC70 (DCK) 6 Ultra Librarian
DSBGA (YZP) 6 Ultra Librarian
USON (DRY) 6 Ultra Librarian
X2SON (DSF) 6 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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