產品詳細資料

Protocols Analog Configuration 1:1 SPST Number of channels 16 Bandwidth (MHz) 500 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Supply current (typ) (µA) 1000 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 64 COFF (typ) (pF) 4 CON (typ) (pF) 10 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 10000 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
Protocols Analog Configuration 1:1 SPST Number of channels 16 Bandwidth (MHz) 500 Ron (typ) (mΩ) 5000 Input/output voltage (min) (V) 0 Input/output voltage (max) (V) 5.5 Supply current (typ) (µA) 1000 Operating temperature range (°C) -40 to 85 ESD CDM (kV) 1 Input/output continuous current (max) (mA) 64 COFF (typ) (pF) 4 CON (typ) (pF) 10 OFF-state leakage current (max) (µA) 1 Ron (max) (mΩ) 10000 VIH (min) (V) 1.7 VIL (max) (V) 0.8 Rating Catalog
TSSOP (DGG) 48 101.25 mm² (12.5 mm × 8.1 mm) TVSOP (DGV) 48 62.08 mm² (9.7 mm × 6.4 mm) SSOP (DL) 48 164.358 mm² (15.88 mm × 10.35 mm)
  • High-Bandwidth Data Path (Up to 500 MHz)(1)
  • 5-V Tolerant I/Os With Device Powered Up or
    Powered Down
  • Low and Flat ON-State Resistance (ron)
    Characteristics Over Operating Range
    (ron= 5 Ω Typical)
  • Rail-to-Rail Switching on Data I/O Ports
    • 0 to 5-V Switching With 3.3-V VCC
    • 0 to 3.3-V Switching With 2.5-V VCC
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low Input and Output Capacitance Minimizes
    Loading and Signal Distortion
    (Cio(OFF) = 4 pF Typical)
  • Fast Switching Frequency (fOE = 20 MHz
    Maximum)
  • Data and Control Inputs Provide Undershoot
    Clamp Diodes
  • Low Power Consumption (ICC = 1 mA Typical)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0 to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or
    5-V and 3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications
  • High-Bandwidth Data Path (Up to 500 MHz)(1)
  • 5-V Tolerant I/Os With Device Powered Up or
    Powered Down
  • Low and Flat ON-State Resistance (ron)
    Characteristics Over Operating Range
    (ron= 5 Ω Typical)
  • Rail-to-Rail Switching on Data I/O Ports
    • 0 to 5-V Switching With 3.3-V VCC
    • 0 to 3.3-V Switching With 2.5-V VCC
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low Input and Output Capacitance Minimizes
    Loading and Signal Distortion
    (Cio(OFF) = 4 pF Typical)
  • Fast Switching Frequency (fOE = 20 MHz
    Maximum)
  • Data and Control Inputs Provide Undershoot
    Clamp Diodes
  • Low Power Consumption (ICC = 1 mA Typical)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0 to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or
    5-V and 3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications

The SN74CB3Q16244 device is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The SN74CB3Q16244 device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q16244 device provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q16244 device is organized as four 4-bit bus switches with separate output-enable (1OE, 2OE, 3OE, 4OE) inputs. It can be used as four 4-bit bus switches, two 8-bit bus switches, or one 16-bit bus switch. When OE is low, the associated 4-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 4-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CB3Q16244 device is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The SN74CB3Q16244 device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q16244 device provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q16244 device is organized as four 4-bit bus switches with separate output-enable (1OE, 2OE, 3OE, 4OE) inputs. It can be used as four 4-bit bus switches, two 8-bit bus switches, or one 16-bit bus switch. When OE is low, the associated 4-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 4-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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重要文件 類型 標題 格式選項 下載最新的英文版本 日期
* 資料表 SN74CB3Q16244 16-Bit FET Bus Switch 2.5-V – 3.3-V Low-Voltage High-Bandwidth Bus Switch datasheet (Rev. A) PDF | HTML 2015/9/18
應用說明 Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022/6/2
應用說明 Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021/12/1
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 2021/1/6

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模擬型號

SN74CB3Q16244 IBIS Model

SCDM075.ZIP (25 KB) - IBIS 模型
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SSOP (DL) 48 Ultra Librarian

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