產品詳細資料

Configuration 1:1 SPST Number of channels 16 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (typ) (Ω) 5 CON (typ) (pF) 10 Supply current (typ) (µA) 1000 Bandwidth (MHz) 500 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Supports input voltage beyond supply Input/output continuous current (max) (mA) 64 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
Configuration 1:1 SPST Number of channels 16 Power supply voltage - single (V) 2.5, 3.3 Protocols Analog Ron (typ) (Ω) 5 CON (typ) (pF) 10 Supply current (typ) (µA) 1000 Bandwidth (MHz) 500 Operating temperature range (°C) -40 to 85 Features Powered-off protection, Supports input voltage beyond supply Input/output continuous current (max) (mA) 64 Rating Catalog Drain supply voltage (max) (V) 3.6 Supply voltage (max) (V) 3.6
SSOP (DL) 48 164.358 mm² 15.88 x 10.35 TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1 TVSOP (DGV) 48 62.08 mm² 9.7 x 6.4
  • High-Bandwidth Data Path (Up to 500 MHz)(1)
  • 5-V Tolerant I/Os With Device Powered Up or
    Powered Down
  • Low and Flat ON-State Resistance (ron)
    Characteristics Over Operating Range
    (ron= 5 Ω Typical)
  • Rail-to-Rail Switching on Data I/O Ports
    • 0 to 5-V Switching With 3.3-V VCC
    • 0 to 3.3-V Switching With 2.5-V VCC
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low Input and Output Capacitance Minimizes
    Loading and Signal Distortion
    (Cio(OFF) = 4 pF Typical)
  • Fast Switching Frequency (fOE = 20 MHz
    Maximum)
  • Data and Control Inputs Provide Undershoot
    Clamp Diodes
  • Low Power Consumption (ICC = 1 mA Typical)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0 to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or
    5-V and 3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications
  • High-Bandwidth Data Path (Up to 500 MHz)(1)
  • 5-V Tolerant I/Os With Device Powered Up or
    Powered Down
  • Low and Flat ON-State Resistance (ron)
    Characteristics Over Operating Range
    (ron= 5 Ω Typical)
  • Rail-to-Rail Switching on Data I/O Ports
    • 0 to 5-V Switching With 3.3-V VCC
    • 0 to 3.3-V Switching With 2.5-V VCC
  • Bidirectional Data Flow With Near-Zero
    Propagation Delay
  • Low Input and Output Capacitance Minimizes
    Loading and Signal Distortion
    (Cio(OFF) = 4 pF Typical)
  • Fast Switching Frequency (fOE = 20 MHz
    Maximum)
  • Data and Control Inputs Provide Undershoot
    Clamp Diodes
  • Low Power Consumption (ICC = 1 mA Typical)
  • VCC Operating Range From 2.3 V to 3.6 V
  • Data I/Os Support 0 to 5-V Signaling Levels
    (0.8 V, 1.2 V, 1.5 V, 1.8 V, 2.5 V, 3.3 V, 5 V)
  • Control Inputs Can Be Driven by TTL or
    5-V and 3.3-V CMOS Outputs
  • Ioff Supports Partial-Power-Down Mode Operation
  • Latch-Up Performance Exceeds 100 mA
    Per JESD 78, Class II
  • ESD Performance Tested Per JESD 22
    • 2000-V Human Body Model
      (A114-B, Class II)
    • 1000-V Charged-Device Model (C101)
  • Supports Both Digital and Analog Applications

The SN74CB3Q16244 device is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The SN74CB3Q16244 device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q16244 device provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q16244 device is organized as four 4-bit bus switches with separate output-enable (1OE, 2OE, 3OE, 4OE) inputs. It can be used as four 4-bit bus switches, two 8-bit bus switches, or one 16-bit bus switch. When OE is low, the associated 4-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 4-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The SN74CB3Q16244 device is a high-bandwidth FET bus switch using a charge pump to elevate the gate voltage of the pass transistor, providing a low and flat ON-state resistance (ron). The low and flat ON-state resistance allows for minimal propagation delay and supports rail-to-rail switching on the data input/output (I/O) ports. The SN74CB3Q16244 device also features low data I/O capacitance to minimize capacitive loading and signal distortion on the data bus. Specifically designed to support high-bandwidth applications, the SN74CB3Q16244 device provides an optimized interface solution ideally suited for broadband communications, networking, and data-intensive computing systems.

The SN74CB3Q16244 device is organized as four 4-bit bus switches with separate output-enable (1OE, 2OE, 3OE, 4OE) inputs. It can be used as four 4-bit bus switches, two 8-bit bus switches, or one 16-bit bus switch. When OE is low, the associated 4-bit bus switch is ON, and the A port is connected to the B port, allowing bidirectional data flow between ports. When OE is high, the associated 4-bit bus switch is OFF, and a high-impedance state exists between the A and B ports.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry prevents damaging current backflow through the device when it is powered down. The device has isolation during power off.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

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類型 標題 日期
* Data sheet SN74CB3Q16244 16-Bit FET Bus Switch 2.5-V – 3.3-V Low-Voltage High-Bandwidth Bus Switch datasheet (Rev. A) PDF | HTML 2015年 9月 18日
Application note Selecting the Correct Texas Instruments Signal Switch (Rev. E) PDF | HTML 2022年 6月 2日
Application note Multiplexers and Signal Switches Glossary (Rev. B) PDF | HTML 2021年 12月 1日
Application note CBT-C, CB3T, and CB3Q Signal-Switch Families (Rev. C) PDF | HTML 2021年 11月 19日
Application brief Eliminate Power Sequencing with Powered-off Protection Signal Switches (Rev. C) PDF | HTML 2021年 1月 6日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
More literature Digital Bus Switch Selection Guide (Rev. A) 2004年 11月 10日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note Bus FET Switch Solutions for Live Insertion Applications 2003年 2月 7日

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模擬型號

SN74CB3Q16244 IBIS Model

SCDM075.ZIP (25 KB) - IBIS Model
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SSOP (DL) 48 檢視選項
TSSOP (DGG) 48 檢視選項
TVSOP (DGV) 48 檢視選項

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