產品詳細資料

Technology family HC Number of channels 2 Operating temperature range (°C) -40 to 125 Rating Automotive Supply current (max) (µA) 80
Technology family HC Number of channels 2 Operating temperature range (°C) -40 to 125 Rating Automotive Supply current (max) (µA) 80
SOIC (D) 16 59.4 mm² 9.9 x 6 TSSOP (PW) 16 32 mm² 5 x 6.4
  • Qualified for Automotive Applications
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive up to Ten LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 10 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
  • ESD Protection Level per AEC-Q100 Classification
    • 2000-V (H2) Human-Body Model
    • 200-V (M3) Machine Model
    • 1000-V (C5) Charged-Device Model

  • Qualified for Automotive Applications
  • Targeted Specifically for High-Speed Memory Decoders and Data-Transmission Systems
  • Wide Operating Voltage Range of 2 V to 6 V
  • Outputs Can Drive up to Ten LSTTL Loads
  • Low Power Consumption, 80-µA Max ICC
  • Typical tpd = 10 ns
  • ±4-mA Output Drive at 5 V
  • Low Input Current of 1 µA Max
  • Incorporate Two Enable Inputs to Simplify Cascading and/or Data Reception
  • ESD Protection Level per AEC-Q100 Classification
    • 2000-V (H2) Human-Body Model
    • 200-V (M3) Machine Model
    • 1000-V (C5) Charged-Device Model

The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable G input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.

The SN74HC139 device is designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay time of this decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The SN74HC139 device comprises two individual 2-line to 4-line decoders in a single package. The active-low enable G input can be used as a data line in demultiplexing applications. This decoder/demultiplexer features fully buffered inputs, each of which represents only one normalized load to its driving circuit.

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類型 標題 日期
* Data sheet Dual 2-Line to 4-Line Decoder/Demultiplexer datasheet (Rev. B) 2008年 4月 24日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
More literature Automotive Logic Devices Brochure 2014年 8月 27日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
User guide Signal Switch Data Book (Rev. A) 2003年 11月 14日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note CMOS Power Consumption and CPD Calculation (Rev. B) 1997年 6月 1日
Application note Designing With Logic (Rev. C) 1997年 6月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note SN54/74HCT CMOS Logic Family Applications and Restrictions 1996年 5月 1日
Application note Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc 1996年 4月 1日

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14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組

14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。

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SOIC (D) 16 Ultra Librarian
TSSOP (PW) 16 Ultra Librarian

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