SN74LV240A
- VCC operation of 2 V to 5.5 V
- Max tpd of 6.5 ns at 5 V
- Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C
- Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C
- Support Mixed-Mode Voltage Operation on All Ports
- Latch-Up Performance Exceeds 250 mA per JESD 17
- Ioff Supports Live Insertion, Partial Power-Down Mode, and Back Drive Protection
These octal buffers/drivers with inverted outputs are designed for 2 V to 5.5 V VCC operation.
The ’LV240A devices are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters.
These devices are organized as two 4-bit buffers/line drivers with separate output-enable ( OE) inputs. When OE is low, the device passes inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state.
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檢視所有 1 類型 | 標題 | 日期 | ||
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* | Data sheet | SN74LV240A Octal Inverting Buffers/Drivers With 3-State Outputs datasheet (Rev. J) | PDF | HTML | 2022年 12月 6日 |
設計與開發
如需其他條款或必要資源,請按一下下方的任何標題以檢視詳細頁面 (如有)。
開發板
14-24-LOGIC-EVM — 適用於 14 針腳至 24 針腳 D、DB、DGV、DW、DYY、NS 和 PW 封裝的邏輯產品通用評估模組
14-24-LOGIC-EVM 評估模組 (EVM) 設計用於支援任何 14 針腳至 24 針腳 D、DW、DB、NS、PW、DYY 或 DGV 封裝的任何邏輯裝置。
封裝 | 引腳 | 下載 |
---|---|---|
SOIC (DW) | 20 | 檢視選項 |
SOP (NS) | 20 | 檢視選項 |
SSOP (DB) | 20 | 檢視選項 |
TSSOP (PW) | 20 | 檢視選項 |
TVSOP (DGV) | 20 | 檢視選項 |
訂購與品質
內含資訊:
- RoHS
- REACH
- 產品標記
- 鉛塗層/球物料
- MSL 等級/回焊峰值
- MTBF/FIT 估算值
- 材料內容
- 資格摘要
- 進行中可靠性監測
內含資訊:
- 晶圓廠位置
- 組裝地點