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SN74LVTH162244-EP

現行

具有匯流排電位保持、TTL 相容 CMOS 輸入和 3 態輸出的增強型產品 16 通道、2.7-V 至 3.6-V 緩衝器

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產品規格表

SN74LVTH162244-EP

現行
產品規格表 立即訂購

產品詳細資料

Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 Supply current (max) (µA) 5000 IOH (max) (mA) -12 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 85
Technology family LVT Supply voltage (min) (V) 2.7 Supply voltage (max) (V) 3.6 Number of channels 16 IOL (max) (mA) 12 Supply current (max) (µA) 5000 IOH (max) (mA) -12 Input type TTL-Compatible CMOS Output type 3-State Features Balanced outputs, Bus-hold, Over-voltage tolerant inputs, Partial power down (Ioff), Power up 3-state, Ultra high speed (tpd <5ns) Rating HiRel Enhanced Product Operating temperature range (°C) -40 to 85
TSSOP (DGG) 48 101.25 mm² 12.5 x 8.1
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Member of the Texas Instruments Widebus™ Family
  • Output Ports Have Equivalent 22- Series Resistors, So No External Resistors Are Required
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Supports Unregulated Battery Operation Down To 2.7 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
Widebus is a trademark of Texas Instruments.
  • Controlled Baseline
    • One Assembly/Test Site, One Fabrication Site
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree
  • Member of the Texas Instruments Widebus™ Family
  • Output Ports Have Equivalent 22- Series Resistors, So No External Resistors Are Required
  • Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
  • Supports Unregulated Battery Operation Down To 2.7 V
  • Typical VOLP (Output Ground Bounce)
       <0.8 V at VCC = 3.3 V, TA = 25°C
  • Ioff and Power-Up 3-State Support Hot Insertion
  • Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
  • Distributed VCC and GND Pins Minimize High-Speed Switching Noise
  • Flow-Through Architecture Optimizes PCB Layout
  • Latch-Up Performance Exceeds 500 mA Per JESD 17
  • ESD Protection Exceeds JESD 22
    • 2000-V Human-Body Model (A114-A)
    • 200-V Machine Model (A115-A)

Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
Widebus is a trademark of Texas Instruments.

The SN74LVTH162244 is a 16-bit buffer and line driver designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides true outputs and symmetrical active-low output-enable (OE)\ inputs.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.

The SN74LVTH162244 is a 16-bit buffer and line driver designed for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment. This device can be used as four 4-bit buffers, two 8-bit buffers, or one 16-bit buffer. This device provides true outputs and symmetrical active-low output-enable (OE)\ inputs.

The outputs, which are designed to source or sink up to 12 mA, include equivalent 22- series resistors to reduce overshoot and undershoot.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, OE\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

This device is fully specified for hot-insertion applications using Ioff and power-up 3-state. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict.
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類型 標題 日期
* Data sheet SN74LVTH162244-EP datasheet 2003年 11月 10日
* VID SN74LVTH162244-EP VID V6204708 2016年 6月 21日
Application note Implications of Slow or Floating CMOS Inputs (Rev. E) 2021年 7月 26日
Selection guide Logic Guide (Rev. AB) 2017年 6月 12日
Application note Understanding and Interpreting Standard-Logic Data Sheets (Rev. C) 2015年 12月 2日
User guide LOGIC Pocket Data Book (Rev. B) 2007年 1月 16日
Application note Semiconductor Packing Material Electrostatic Discharge (ESD) Protection 2004年 7月 8日
Application note TI IBIS File Creation, Validation, and Distribution Processes 2002年 8月 29日
Application note 16-Bit Widebus Logic Families in 56-Ball, 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B) 2002年 5月 22日
Application note Power-Up 3-State (PU3S) Circuits in TI Standard Logic Devices 2002年 5月 10日
Selection guide Advanced Bus Interface Logic Selection Guide 2001年 1月 9日
Application note LVT-to-LVTH Conversion 1998年 12月 8日
Application note LVT Family Characteristics (Rev. A) 1998年 3月 1日
Application note Bus-Interface Devices With Output-Damping Resistors Or Reduced-Drive Outputs (Rev. A) 1997年 8月 1日
Application note Input and Output Characteristics of Digital Integrated Circuits 1996年 10月 1日
Application note Live Insertion 1996年 10月 1日
Application note Understanding Advanced Bus-Interface Products Design Guide 1996年 5月 1日

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