產品詳細資料

Bits (#) 8 Data rate (max) (Mbps) 420 Vin (min) (V) 1.1 Vin (max) (V) 5.5 Vout (min) (V) 1.1 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Bus-hold, Integrated pulldown resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc disconnect, Vcc isolation Prop delay (ns) 7.5 Technology family LXC Supply current (max) (mA) 0.012 Rating Catalog Operating temperature range (°C) -40 to 125
Bits (#) 8 Data rate (max) (Mbps) 420 Vin (min) (V) 1.1 Vin (max) (V) 5.5 Vout (min) (V) 1.1 Vout (max) (V) 5.5 Applications GPIO, JTAG, SPI, UART Features Bus-hold, Integrated pulldown resistors, Output enable, Overvoltage tolerant inputs, Partial power down (Ioff), Vcc disconnect, Vcc isolation Prop delay (ns) 7.5 Technology family LXC Supply current (max) (mA) 0.012 Rating Catalog Operating temperature range (°C) -40 to 125
TSSOP (PW) 24 49.92 mm² 7.8 x 6.4 VQFN (RHL) 24 19.25 mm² 5.5 x 3.5
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate from 1.1 V to 5.5 V
  • Robust, Glitch-Free Power Supply Sequencing
  • Up to 420-Mbps Support for 3.3 V to 5.0 V
  • Bus Hold on Data Inputs Eliminates the Need for External Pull-Up and Pull-Down Resistors
  • Schmitt-Trigger Control Inputs Allow for Slow or Noisy Inputs
  • Control Inputs with Integrated Static Pull-Down Resistors Allow for Floating Control Inputs
  • High Drive Strength (up to 32 mA at 5 V)
  • Low Power Consumption
    • 4-µA Maximum (25°C)
    • 12-µA Maximum (–40°C to 125°C)
  • VCC Isolation and VCC Disconnect feature
    • If Either VCC Supply is < 100 mV All I/O’s Become High-Impedance
    • Ioff-float Supports VCC Disconnect Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Compatible with LVC Family Level Shifters
  • Control Logic (DIR and OE) are Referenced to VCCA
  • Operating Temperature from –40°C to +125°C
  • Latch-Up Performance Exceeds 100 mA per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model
    • 1000-V Charged-Device Model
  • Fully Configurable Dual-Rail Design Allows Each Port to Operate from 1.1 V to 5.5 V
  • Robust, Glitch-Free Power Supply Sequencing
  • Up to 420-Mbps Support for 3.3 V to 5.0 V
  • Bus Hold on Data Inputs Eliminates the Need for External Pull-Up and Pull-Down Resistors
  • Schmitt-Trigger Control Inputs Allow for Slow or Noisy Inputs
  • Control Inputs with Integrated Static Pull-Down Resistors Allow for Floating Control Inputs
  • High Drive Strength (up to 32 mA at 5 V)
  • Low Power Consumption
    • 4-µA Maximum (25°C)
    • 12-µA Maximum (–40°C to 125°C)
  • VCC Isolation and VCC Disconnect feature
    • If Either VCC Supply is < 100 mV All I/O’s Become High-Impedance
    • Ioff-float Supports VCC Disconnect Operation
  • Ioff Supports Partial-Power-Down Mode Operation
  • Compatible with LVC Family Level Shifters
  • Control Logic (DIR and OE) are Referenced to VCCA
  • Operating Temperature from –40°C to +125°C
  • Latch-Up Performance Exceeds 100 mA per JESD 78, Class II
  • ESD Protection Exceeds JESD 22
    • 4000-V Human-Body Model
    • 1000-V Charged-Device Model

The SN74LXCH8T245 is an 8-bit, dual-supply noninverting bidirectional voltage level translation device with bus-hold circuitry. Ax pins and control pins (DIR and OE) are referenced to VCCA logic levels, and Bx pins are referenced to VCCB logic levels. The A port is able to accept I/O voltages ranging from 1.1 V to 5.5 V, while the B port can accept I/O voltages from 1.1 V to 5.5 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both Ax and Bx pins are in the high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.

The SN74LXCH8T245 is an 8-bit, dual-supply noninverting bidirectional voltage level translation device with bus-hold circuitry. Ax pins and control pins (DIR and OE) are referenced to VCCA logic levels, and Bx pins are referenced to VCCB logic levels. The A port is able to accept I/O voltages ranging from 1.1 V to 5.5 V, while the B port can accept I/O voltages from 1.1 V to 5.5 V. A high on DIR allows data transmission from A to B and a low on DIR allows data transmission from B to A when OE is set to low. When OE is set to high, both Ax and Bx pins are in the high-impedance state. See Device Functional Modes for a summary of the operation of the control logic.

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重要文件 類型 標題 格式選項 日期
* Data sheet SN74LXCH8T245 8-bit Translating Transceiver with Configurable Level Shifting datasheet (Rev. B) PDF | HTML 2021年 3月 15日
Application note Schematic Checklist - A Guide to Designing With Fixed or Direction Control Translators PDF | HTML 2024年 10月 2日
Application note Schematic Checklist - A Guide to Designing with Auto-Bidirectional Translators PDF | HTML 2024年 7月 12日
Application note Understanding Transient Drive Strength vs. DC Drive Strength in Level-Shifters (Rev. A) PDF | HTML 2024年 7月 3日
Application brief Bringing Together 5G Signal Chains With Level Translation PDF | HTML 2021年 3月 5日

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開發板

AVCLVCDIRCNTRL-EVM — 適用於方向控制雙向轉換裝置、支援 AVC 和 LVC 的通用 EVM

通用 EVM 的設計可支援一、二、四、八通道 LVC 及 AVC 方向控制的轉換裝置。此外也支援相同通道數量的匯流排保留與汽車 -Q1 裝置。AVC 是低電壓轉換裝置,具較低驅動強度 12mA。LVC 是較高的電壓轉換裝置,範圍從 1.65 到 5.5V 且具較高驅動強度 32mA。

使用指南: PDF
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封裝 針腳 CAD 符號、佔位空間與 3D 模型
TSSOP (PW) 24 Ultra Librarian
VQFN (RHL) 24 Ultra Librarian

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