封裝資訊
| 封裝 | 引腳 VSSOP (DGK) | 8 |
| 作業溫度範圍 (°C) -40 to 125 |
| 包裝數量 | 運送包裝 80 | TUBE |
TPS773 的特色
- Open Drain Power-On Reset With 220-ms Delay (TPS773xx)
- Open Drain Power-Good (PG) Status Output (TPS774xx)
- 250-mA Low-Dropout Voltage Regulator
- Available in 1.5-V, 1.6-V (TPS77316 Only), 1.8-V, 2.7-V, 2.8-V, 3.3-V, 5.0-V Fixed Output and Adjustable Versions
- Dropout Voltage Typically 200 mV at 250 mA (TPS77333, TPS77433)
- Ultralow 92-uA Quiescent Current (Typ)
- 8-Pin MSOP (DGK) Package
- Low Noise (55 uVrms) Without an External Filter (Bypass) Capacitor (TPS77318, TPS77418)
- 2% Tolerance Over Specified Conditions For Fixed-Output Versions
- Fast Transient Response
- Thermal Shutdown Protection
- See the TPS779xx Family of Devices for Active High Enable
TPS773 的說明
The TPS773xx and TPS774xx are low-dropout regulators with integrated power-on reset and power good (PG) function respectively. These devices are capable of supplying 250 mA of output current with a dropout of 200 mV (TPS77333, TPS77433). Quiescent current is 92 uA at full load dropping down to 1 uA when device is disabled. These devices are optimized to be stable with a wide range of output capacitors including low ESR ceramic (10 uF) or low capacitance (1 uF) tantalum capacitors. These devices have extremely low noise output performance (55 uVrms) without using any added filter capacitors. TPS773xx and TPS774xx are designed to have fast transient response for larger load current changes.
The TPS773xx or TPS774xx is offered in 1.5-V, 1.6 V (TPS77316 only), 1.8-V, 2.7-V, 2.8-V, 3.3-V, and 5.0-V fixed-voltage versions and in an adjustable version (programmable over the range of 1.5 V to 5.5 V). Output voltage tolerance is 2% over line, load, and temperature ranges. The TPS773xx and TPS774xx families are available in 8-pin MSOP (DGK) packages.
Because the PMOS device behaves as a low-value resistor, the dropout voltage is very low (typically 200 mV at an output current of 250 mA for 3.3-volt option) and is directly proportional to the output current. Additionally, since the PMOS pass element is a voltage-driven device, the quiescent current is very low and independent of output loading (typically 92 uA over the full range of output current, 0 mA to 250 mA). These two key specifications yield a significant improvement in operating life for battery-powered systems.
The device is enabled when the EN\ pin is connected to a low-level input voltage. This LDO family also features a sleep mode; applying a TTL high signal to EN\ (enable) shuts down the regulator, reducing the quiescent current to less than 1 uA at T J = 25°C.
The TPS773xx features an integrated power-on reset, commonly used as a supply voltage supervisor (SVS), or reset output voltage. The RESET\ output of the TPS773xx initiates a reset in DSP, microcomputer or microprocessor systems at power up and in the event of an undervoltage condition. An internal comparator in the TPS773xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT reaches 95% of its regulated voltage, RESET\ will go to a high-impedance state after a 220-ms delay. RESET\ will go to low-impedance state when OUT is pulled below 95% (i.e. over load condition) of its regulated voltage.
For the TPS774xx, the power good terminal (PG) is an active high output, which can be used to implement a power-on reset or a low-battery indicator. An internal comparator in the TPS774xx monitors the output voltage of the regulator to detect an undervoltage condition on the regulated output voltage. When OUT falls below 82% of its regulated voltage, PG will go to a low-impedance state. PG will go to a high-impedance state when OUT is above 82% of its regulated voltage.