Texas Instruments TMS320C64x™ Digital Signal Processors
TI's TMS320C64x DSPs are based on the C64x™ DSP core, with its scalable very-long-instruction-word (VLIW) architecture. The C64x generation is designed for third-generation (3G) wireless and broadband infrastructure, as well as imaging/video applications.
Operating frequencies: 400-, 500- and 600-MHz versions
Process: 0.12-micron CMOS
Voltages: 1.2-V core, 3.3-V I/Os
Power consumption: Less than 1W for entire chip minus I/O in typical operation
Hardware accelerators (C6416 only): Viterbi coprocessor (VCP) for 200+ voice channels, Turbo coprocessor (TCP) for three 2-Mbps channels
On-chip cache memory: 16 kbytes level 1 data, 16 kbytes level 1 program; 1024 kbytes (8 Mbits) level 2 unified program and data with four ways individually reprogrammable as direct-mapped blocks
External memory control and I/O: 32-channel enhanced DMA (EDMA), 64-bit enhanced memory interface (EMIF), 16-bit EMIF for searcher/rake receiver
Communications I/O peripherals (C6415 and C6416 only): 32-bit PCI/AHPI, 8-bit Utopia II
Other peripherals: Multichannel buffered serial ports (McBSPs--three in C6414, two in C6415 and C6416); 32 multiplexed general-purpose I/O; three timers
Testing/debug: Enhanced JTAG port with Real-Time Data Exchange (RTDX™)
Package: 532-lead 23x23-mm BGA
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