Adding an LDO for Increased Standby Mode Efficiency Reference Design
TIDA-00393
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Key Document
- Adding an LDO for Increased Standby Mode Efficiency Design Guide
(PDF 1196 KB)
07 Jul 2015
Description
This regulation topology is designed to increase the efficiency of a DC/DC buck converter by disabling the converter during light-load operation and providing a regulated output voltage with a low-Iq LDO. During no-load or light-load conditions, the LDO allows for low-noise, low-Iq output voltage regulation while the DC/DC is disabled. Once the load is engaged, the DC/DC converter can provide high efficiency at high load currents, thereby combining the benefits of both devices.
Features
- High Efficiency output regulation from no load to full load (3A)
- Ultra-low Iq with no load regulation (<15 uA)
- DC/DC output ripple less than 10mV peak to peak
- LDO output noise less than 200 uV RMS, 10Hz to 100kHz
- 3.3% Transient Droop @ 1.2V, 300mA to 3A, 1A/ms
See the Important Notice and Disclaimer covering reference designs and other TI resources.