Battery-powered Data Collector for wM-Bus T-/C-mode & DSSS-coded Data Packets @ 868.95MHz Ref Design
TIDC-DSSS868WMBUS-DC enables data collectors with optimized firmware for receiving wireless M-Bus (wM-Bus) packets in frequent transmission (T-) and compact (C-) modes at 868.95 MHz. For improved range, a customized direct sequence spread spectrum (DSSS)-coded packet reception is also supported. This reference design can be adapted for wM-Bus and DSSS-enabled data collectors and mobile readers at 169-MHz and 433-MHz bands.
- Battery-powered data collector (or Mobile reader) for wM-Bus T- and C-mode or DSSS-coded data packets
- 10 Vin ultra-low Iq DC/DC supports multiple battery types, configurations and chemistries.
- Market leading blocking, selectivity and RX sensitivity in wM-Bus T-mode with +-12% data rate variation with 100 kcps @ 868.95 MHz for a robust wireless design
- EN13757-4 T- and C-mode compliant "other" device with open source code examples for receive operation
- 11-bits (and 16-bits) DSSS-coding of data supported in hardware
- This ultra low-power, battery-operated data collector system is tested and includes open source licensed firmware. It also includes SRF7 studio GUI configuration files and user's guide and our sub-1 GHz transceiver, MSP430 microcontroller and ultra-low Iq step--down converter.
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Design files & products
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Reference design overview and verified performance test data
Detailed schematic diagram for design layout and components
Complete listing of design components, reference designators, and manufacturers/part numbers
Detailed overview of design layout for component placement
Files used for 3D models or 2D drawings of IC components
Design file that contains information on physical board layer of design PCB
PCB layer plot file used for generating PCB design layout
Includes TI products in the design and potential alternatives.
MSP430F5438A — 25-MHz MCU with 256-KB flash, 16-KB SRAM, 12-bit ADC, DMA, UART/SPI/I2C, timer, HW multiplierData sheet: PDF | HTML
|*||Design guide||Data Collector for wM-Bus T-/C-Modes and DSSS-Coded Long-Range Mode Design Guide (Rev. A)||May 26, 2017|
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