TIPD112
Data Acquisition for MUX and Step Inputs, 18 bits, 1uS Full Scale Response Reference Design
TIPD112
Overview
This TI Verified Design is a high performance data acquisition system (DAQ) using an 18-bit SAR ADC, ADS8881 at a throughput of 1MSPS. This design has been optimized to provide 18-bit settling performance for a Full Scale Step Input signal, thus leading to excellent system linearity. Such an input stimulus is more applicable in MUXed applications for transition between channels with different input voltages. The input driver for the ADC uses the OPA350 for high bandwidth (small & large signal), output current drive and linear rail-to-rail input and output operation. The reference buffer drive utilizes a composite buffer made out of THS4281 & OPA333 to get the desired performance at lowest power consumption. This DAQ block achieves a ±2.5LSB INL performance for a total power consumption of less than 70mW.
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Features
- 18 Bit, 1Msps Sampling Rate
- DC, MUX'ed, and Full Scale Step Inputs
- Optimization: Transient Settling
- Power: 70mW @ AVDD = 5V
- Utilizes ADS8881 (18bit, 1Msps SAR ADC), OPA2350 (Input), THS4281 + OPA333 + REF5045 (Reference)
Industrial
A fully assembled board has been developed for testing and performance validation only, and is not available for sale.
Design files & products
Design files
Download ready-to-use system files to speed your design process.
TIDR116B.PDF (172 K)
Detailed schematic diagram for design layout and components
SLAC582.ZIP (1882 K)
Detailed schematic diagram for design layout and components
TIDR115B.PDF (103 K)
Complete listing of design components, reference designators, and manufacturers/part numbers
TIDC011A.ZIP (1436 K)
Design file that contains information on physical board layer of design PCB
Products
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Technical documentation
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| Type | Title | Date | ||
|---|---|---|---|---|
| * | User guide | 18-Bit Data Acquisition (DAQ) Block Optimized for 1-μs Full-Scale Step Response (Rev. C) | Feb. 02, 2017 |
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