DAC Sample and Hold Glitch Reduction Reference Design


Design files


DAC R-2R architectures display great performance in regards to noise and accuracy, but at a cost of large glitch area. This design focuses on the reduction of major-carry glitches that occur from code specific transitions in DAC R-2R architectures. This design reduces this glitch area, making it suitable for glitch-sensitive applications such as waveform generation.

  • 18-bit, 0-5 V output
  • R-2R DAC with S&H Glitch Reduction Circuitry
  • <0.015 %FSR total unadjusted error
  • <2 LSB INL
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A fully assembled board has been developed for testing and performance validation only, and is not available for sale.

Design files & products

Design files

Download ready-to-use system files to speed your design process.


Detailed schematic diagram for design layout and components

TIDC212.ZIP (1399 K)

Detailed schematic diagram for design layout and components


Complete listing of design components, reference designators, and manufacturers/part numbers


Includes TI products in the design and potential alternatives.

Precision DACs (≤10 MSPS)

DAC988118-bit, single-channel, low-noise, voltage output DAC for high accuracy applications

Data sheet: PDF | HTML
Analog switches & muxes

TS12A451512-V, 1:1 (SPST), 1-channel general-purpose analog switch (active low)

Data sheet: PDF
Precision op amps (Vos<1mV)

OPA219236-V, Precision, RRIO, Low Offset Voltage, Low Input Bias Current Op Amp With e-trim

Data sheet: PDF | HTML

Technical documentation

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Type Title Date
* User guide Sample & Hold Glitch Reduction for Precision Outputs Design Guide Dec. 10, 2013

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