Power-optimized 16-bit 1MSPS Data Acquisition Block for Lowest Distortion and Noise Reference Design
TIPD149
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See the Important Notice and Disclaimer covering reference designs and other TI resources.
Key Document
- Power-Optimized 16-Bit 1-MSPS Data Acquisition Block Design Guide
(PDF 1771 KB)
10 Dec 2013
-
TIPD149 Design File
(ZIP 1095 KB)
10 Dec 2013
Description
This TI Verified Design is the realization of a high precision, 16-bit 1MSPS data acquisition system suitable for applications such as digital audio that require front-ends with very low distortion and noise. The circuit uses a high performance Successive Approximation Register Analog to Digital Converter (SAR ADC) and has been optimized to provide superior dynamic performance, without excessive power consumption.
Features
- Verified Design Contains Theory, Component Selection, TINA-TI Simulation, Altium Schematics and PCB Layout, Measurement Results
- 16 bit SAR ADC with 1MSPS sampling rate and full-scale input range (FSR) of 4.096V
- Optmized for AC performance:
- -110dB measured THD
- 91.6dB measured SNR
- Less than ±0.5LSB INL
See the Important Notice and Disclaimer covering reference designs and other TI resources.