2-A Peak Sink/Source DDR Termination Regulator With VTTREF Buffered Reference
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- TPS51206EVM-745 User's Guide
(PDF 1281 KB)
05 Aug 2011
The TPS51206EVM-745 evaluation module (EVM) uses the TPS51206. The TPS51206 is a sink/source double data rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low cost, low external component count systems where space is a key consideration. The TPS51206EVM-745 is designed to provide proper termination voltage and a 10-mA buffered reference voltage for DDR memory which covers DDR2 (0.9VTT), DDR3 (0.75VTT), DDR3L (0.675VTT) and DDR4 (0.6VTT) specifications with minimal external components
- VDD voltage: support 5-V rail and 3.3-V rail
- VLDOIN, VDDQ voltage range: 1.2 V–1.8 V
- Build-in, onboard transient load (with both sinking and sourcing capability) to emulate the sink/source transient behavior which helps to evaluate the dynamic performance. For ease of use, both load step and timing of transient can be modified by onboard resistors.
- Switch S1, S2 for S3 and S5 Enable function
- Convenient test points for probing VTT, VTTREF, CLK_IN and loop response testing
- Four-layer, printed-circuit board (PCB) with all the components on the bottom side