Product details

DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Iout VTT (Max) (A) 2 Iq (Typ) (mA) 0.17 Output VREF, VTT Vin (Min) (V) 1 Vin (Max) (V) 3.5 Features S3/S5 Support Rating Catalog
DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Iout VTT (Max) (A) 2 Iq (Typ) (mA) 0.17 Output VREF, VTT Vin (Min) (V) 1 Vin (Max) (V) 3.5 Features S3/S5 Support Rating Catalog
WSON (DSQ) 10 4 mm² 2 x 2
  • Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail
  • VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V
  • VTT Termination Regulator
    • Output Voltage Range: 0.5 V to 0.9 V
    • 2-A Peak Sink and Source Current
    • Requires Only 10-µF MLCC Output Capacitor
    • ±20 mV Accuracy
  • VTTREF Buffered Reference
    • VDDQ/2 ± 1% Accuracy
    • 10-mA Sink and Source Current
  • Supports High-Z in S3 and Soft-Stop in S4 and S5 with S3 and S5 Inputs
  • Overtemperature Protection
  • 10-Pin, 2 mm × 2 mm SON (DSQ) Package
  • Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail
  • VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V
  • VTT Termination Regulator
    • Output Voltage Range: 0.5 V to 0.9 V
    • 2-A Peak Sink and Source Current
    • Requires Only 10-µF MLCC Output Capacitor
    • ±20 mV Accuracy
  • VTTREF Buffered Reference
    • VDDQ/2 ± 1% Accuracy
    • 10-mA Sink and Source Current
  • Supports High-Z in S3 and Soft-Stop in S4 and S5 with S3 and S5 Inputs
  • Overtemperature Protection
  • 10-Pin, 2 mm × 2 mm SON (DSQ) Package

The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration. The device maintains fast transient response and only requires 1 × 10-µF of ceramic output capacitance. The device supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The VTT current capability is ±2-A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4 or S5 state (suspend to disk).

The TPS51206 device is available in 10-Pin, 2 mm × 2 mm SON (DSQ) PowerPAD™ package and specified from –40°C to 105°C.

The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration. The device maintains fast transient response and only requires 1 × 10-µF of ceramic output capacitance. The device supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The VTT current capability is ±2-A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4 or S5 state (suspend to disk).

The TPS51206 device is available in 10-Pin, 2 mm × 2 mm SON (DSQ) PowerPAD™ package and specified from –40°C to 105°C.

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Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS51206EVM-745 — 2-A Peak Sink/Source DDR Termination Regulator With VTTREF Buffered Reference

The TPS51206EVM-745 evaluation module (EVM) uses the TPS51206. The TPS51206 is a sink/source double data rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low cost, low external component count systems where space is a key (...)

User guide: PDF
Not available on TI.com
Simulation model

TPS51206 PSpice Transient Model

SLUM198.ZIP (56 KB) - PSpice Model
Simulation model

TPS51206 TINA-TI Transient Reference Design

SLUM249.TSC (142 KB) - TINA-TI Reference Design
Simulation model

TPS51206 TINA-TI Transient Spice Model

SLUM248.ZIP (42 KB) - TINA-TI Spice Model
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Reference designs

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This reference design features multiple TPS54325 and other power devices for Xilinx Zynq FPGA. From 12-V input, this reference design has the power rails required by Zynq FPGA, including DDR3 memory.
Test report: PDF
Schematic: PDF
Package Pins Download
WSON (DSQ) 10 View options

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