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EVALUATION BOARD Download 49
SIMULATION MODEL Download
The TPS51206EVM-745 evaluation module (EVM) uses the TPS51206. The TPS51206 is a sink/source double data rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low cost, low external component count systems where space is a key (...)
- VDD voltage: support 5-V rail and 3.3-V rail
- VLDOIN, VDDQ voltage range: 1.2 Vâ1.8 V
- Build-in, onboard transient load (with both sinking and sourcing capability) to emulate the sink/source transient behavior which helps to evaluate the dynamic performance. For ease of use, both load step and timing of (...)
SLUM198.ZIP (56 KB) - PSpice Model SIMULATION MODEL Download
SLUM248.ZIP (42 KB) - TINA-TI Spice Model SIMULATION MODEL Download
SLUM249.TSC (142 KB) - TINA-TI Reference Design REFERENCE DESIGNS Download REFERENCE DESIGNS Download REFERENCE DESIGNS Download
Power Solution for Xilinx FPGA Zynq 7 (1.8V@0.15A)
PMP8251 — This reference design features multiple TPS54325 and other power devices for Xilinx Zynq FPGA. From 12-V input, this reference design has the power rails required by Zynq FPGA, including DDR3 memory.