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Product details

Parameters

DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3 Control mode Iout VTT (Max) (A) 2 Iq (Typ) (mA) 0.17 Output VREF, VTT Vin (Min) (V) 1 Vin (Max) (V) 3.5 Features S3/S5 Support Rating Catalog Operating temperature range (C) -40 to 105 open-in-new Find other DDR memory power ICs

Package | Pins | Size

WSON (DSQ) 10 4 mm² 2 x 2 open-in-new Find other DDR memory power ICs

Features

  • Supply Input Voltage: Supports 3.3-V Rail and 5-V Rail
  • VLDOIN Input Voltage Range: VTT+0.4 V to 3.5 V
  • VTT Termination Regulator
    • Output Voltage Range: 0.5 V to 0.9 V
    • 2-A Peak Sink and Source Current
    • Requires Only 10-µF MLCC Output Capacitor
    • ±20 mV Accuracy
  • VTTREF Buffered Reference
    • VDDQ/2 ± 1% Accuracy
    • 10-mA Sink and Source Current
  • Supports High-Z in S3 and Soft-Stop in S4 and S5 with S3 and S5 Inputs
  • Overtemperature Protection
  • 10-Pin, 2 mm × 2 mm SON (DSQ) Package
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Description

The TPS51206 device is a sink and source double date rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low-cost, low-external component count systems where space is a key consideration. The device maintains fast transient response and only requires 1 × 10-µF of ceramic output capacitance. The device supports a remote sensing function and all power requirements for DDR2, DDR3 and Low-Power DDR3 (DDR3L), and DDR4 VTT bus. The VTT current capability is ±2-A peak. The device supports all of the DDR power states, putting VTT to High-Z in S3 state (suspend to RAM) and discharging VTT and VTTREF in S4 or S5 state (suspend to disk).

The TPS51206 device is available in 10-Pin, 2 mm × 2 mm SON (DSQ) PowerPAD™ package and specified from –40°C to 105°C.

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Technical documentation

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Type Title Date
* Data sheet TPS51206 2-A Peak Sink / Source DDR Termination Regulator With VTTREF Buffered Reference for DDR2, DDR3, DDR3L, and DDR4 datasheet (Rev. E) Jul. 19, 2018
Application note Non-Isolated Point-of-Load Solutions for Tiger Lake in PC Applications (Rev. B) Apr. 29, 2021
Application note DDR VTT Power Solutions: A Competitive Analysis (Rev. A) Jul. 09, 2020
Selection guide Power Management Guide 2018 (Rev. R) Jun. 25, 2018
More literature Computing DDR DC-DC Power Solutions Aug. 22, 2012
User guide TPS51206EVM-745 User's Guide Aug. 05, 2011
Application note Pwr Ref Design f/'C6472 12-Vin Digital Pwr Controllers and LDOs Apr. 28, 2010
Application note Power Two Xilinx(TM) LX240 Virtex-6(TM) Devices Apr. 20, 2010
Application note Power Ref Design for TMS320C6472 5Vin DC/DC Converters (1x C6472) Mar. 31, 2010
Application note 'C6472 12Vin Flexible Pwr Design Using DCDC Controllers and LDOs (8x C6472) Mar. 26, 2010
Application note Power Reference Design for the 'C6472, 12V DCDC Controllers, and LDOs Mar. 26, 2010
Application note TMS320C6472 5V Input Pwr Design, Integrated FET DC/DC Converters and Controllers Mar. 26, 2010

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Hardware development

EVALUATION BOARD Download
document-generic User guide
49
Description

The TPS51206EVM-745 evaluation module (EVM) uses the TPS51206. The TPS51206 is a sink/source double data rate (DDR) termination regulator with VTTREF buffered reference output. It is specifically designed for low-input voltage, low cost, low external component count systems where space is a key (...)

Features
  • VDD voltage: support 5-V rail and 3.3-V rail
  • VLDOIN, VDDQ voltage range: 1.2 V–1.8 V
  • Build-in, onboard transient load (with both sinking and sourcing capability) to emulate the sink/source transient behavior which helps to evaluate the dynamic performance. For ease of use, both load step and timing of (...)

Design tools & simulation

SIMULATION MODEL Download
SLUM198.ZIP (56 KB) - PSpice Model
SIMULATION MODEL Download
SLUM248.ZIP (42 KB) - TINA-TI Spice Model
SIMULATION MODEL Download
SLUM249.TSC (142 KB) - TINA-TI Reference Design

Reference designs

REFERENCE DESIGNS Download
High efficiency power supply architecture reference design for protection relay processor module
TIDA-010011 — This reference design showcases various power architectures for generating multiple voltage rails for an application processor module, requiring >1A load current and high efficiency . The required power supply is generated using 5-, 12- or 24-V DC input from the backplane. Power supplies are (...)
document-generic Schematic
REFERENCE DESIGNS Download
Ultra-low Stand-by Power, High-efficiency, DC-DC Power Supply Reference Design for Set-top Box
PMP21065 The PMP21065 Reference design operates off a typical 12V DC input to produce several common rails seen in set top boxes today. The key objectives of the design are to be low-cost, small in size and low stand-by power with high efficiency to help customers meet compliance to new regulatory guidelines (...)
document-generic Schematic
REFERENCE DESIGNS Download
Power Solution for Xilinx FPGA Zynq 7 (1.8V@0.15A)
PMP8251 This reference design features multiple TPS54325 and other power devices for Xilinx Zynq FPGA. From 12-V input, this reference design has the power rails required by Zynq FPGA, including DDR3 memory.
document-generic Schematic

CAD/CAE symbols

Package Pins Download
WSON (DSQ) 10 View options

Ordering & quality

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  • MSL rating/Peak reflow
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  • Qualification summary
  • Ongoing reliability monitoring

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