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ADS98XX-FPGA-EXAMPLE-CODE

ADS98xx FPGA interface example code

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Latest version
Version: 1.1.0
Release date: Feb 8, 2024
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ADS98xx_verilog_source_v1.1.0.zip  — 43 K

Source code archive

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Products
Precision ADCs
ADS9803 — 20-bit eight-channel 2 MSPS per channel simultaneous sampling ADC with programmable gain amplifier ADS9810 — 8-channel, 18-bit, 1MSPS, ±16 ppm INL simultaneous sampling ADC with integrated front end ADS9811 — 8-channel, 18-bit, 1MSPS simultaneous sampling ADC with integrated analog front end ADS9813 — Eight-channel, 18-bit, 2-MSPS/ch simultaneous sampling ADC with integrated analog front end ADS9815 — Eight-channel, 18-bit, 1-MSPS/ch dual simultaneous-sampling ADC with integrated analog front end ADS9817 — Eight-channel, 18-bit, 2-MSPS/ch dual simultaneous-sampling ADC with integrated analog front end

Documentation

open-in-new

Manifest

Manifest

Release Information

Verilog modules for interfacing to the ADS98xx.

What's new

  • v1.0.0 - Initial release
  • v1.1.0 - Moved posedge_detect module to it own file and updated coding-style