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ADS98XX-FPGA-EXAMPLE-CODE

ADS98xx FPGA interface example code

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Latest version
Version: 1.1.0
Release date: 08 Feb 2024
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ADS98xx_verilog_source_v1.1.0.zip  — 43 K

Source code archive

MD5 checksum
Products
Precision ADCs
ADS9817 — Eight-channel, 18-bit, 2-MSPS/ch dual simultaneous-sampling ADC with integrated analog front end

Documentation

open-in-new

Manifest

Manifest

Release Information

Verilog modules for interfacing to the ADS98xx.

What's new

  • v1.0.0 - Initial release
  • v1.1.0 - Moved posedge_detect module to it own file and updated coding-style