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MCU-PLUS-SDK-AM64X

MCU+ SDK for AM64x – RTOS, No-RTOS

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Version: 08.04.00.17
Release date: 30 Sep 2022
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Release notes

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View software details

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mcu_plus_sdk_am64x_08_04_00_17-windows-x64-installer.exe  — 110958 K

MCU PLUS SDK Windows Installer

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mcu_plus_sdk_am64x_08_04_00_17-linux-x64-installer.run  — 110672 K

MCU PLUS SDK Linux Installer

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Products
Arm-based processors
AM6411 — Single-core 64-bit Arm® Cortex®-A53, single-core Cortex-R5F, PCIe, USB 3.0 and security AM6412 — Dual-core 64-bit Arm® Cortex®-A53, single-core Cortex-R5F, PCIe, USB 3.0 and security AM6421 — Single-core 64-bit Arm® Cortex®-A53, dual-core Cortex-R5F, PCIe, USB 3.0 and security AM6441 — Single-core 64-bit Arm® Cortex®-A53, quad-core Cortex-R5F, PCIe, USB 3.0 and security AM6442 — Dual-core 64-bit Arm® Cortex®-A53, quad-core Cortex-R5F, PCIe, USB 3.0 and security

Documentation

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Documentation

Documentation - START HERE

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mcu_plus_sdk_am64x_08_04_00_17_docs_only.tar.xz

Documentation Only Package

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CCS Download Home Page

Download CCS 12.0.0 Version for Windows or Linux

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TI ARM CLANG

Download TI ARM CLANG 2.1.1 LTS for Windows or Linux

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sysconfig-1.13.0_2553-setup.exe

SysConfig Windows Installer

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sysconfig-1.13.0_2553-setup.run

SysConfig Linux Installer

Release Information

Thank you for your interest in the AM64x MCU PLUS Software Development Kit (SDK). This software accelerates application development schedules by eliminating the need to create basic system software functions from scratch.

  • The SDK includes a real-time multitasking kernel, network communications support, examples, and drivers.
  • The exact content of the SDK depends on the capabilities of the device, but all devices share common APIs and build on existing proven software components to ensure reliability and quality.
  • The software components are fully tested to ensure that they work together with TI’s Code Composer Studio integrated development environment.

What's new

  • SR 2.0 HS-FS device support
  • Syconfig support and flash driver redesign to enable new flash configuration
  • Warm reset workaround for CPSW register lockup in MMCSD and OSPI SBL
  • CPSW: TCP/IP Checksum offload, DSCP Priority mapping and Policer usecase, Multi-core (R5) support, Simplified LwIP CPSW examples, CPSW ALE configurations via SysConfig
  • CPSW driver memory footprint reduced by more than 40% 
  • MDIO Manual Mode Support for CPSW, EtherCAT Slave Beckhoff SSC examples and HSR-PRP examples
  • HSR(High-availability Seamless Redundancy) example
  • Optimized trigonometric function support on R5 core
  • SDL: MCRC and ESM