CDCLVP1102EVM
CDCLVP1102 評価モジュール
CDCLVP1102EVM
概要
The CDCLVP1102 is a high-performance, low additive phase noise clock buffer. It has a single universal input buffer that supports either single-ended or differential clock inputs, and feeds to two LVPECL outputs. The device also features on-chip bias generators that can provide the LVPECL common-mode voltage to the device inputs. This evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVP1102. This fully assembled and factory-tested evaluation board allows complete validation of the CDCLVP1102 device functionalities. For optimum performance, the board is equipped with 50-W SMA connectors and well-controlled, 50-W impedance microstrip transmission lines.
特長
- Easy-to-use evaluation board to fan out low phase noise clocks
- Easy device setup
- Fast configuration
- Control pins configurable through jumpers
- Board powered at +2.5-/+3.3-V
- Single-ended or differential input clocks
- CDCLVP1102 supports two LVPECL outputs; CDCLVP1102EVM supports one LVPECL output
クロック・バッファ
技術資料
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すべて表示 2
| 種類 | タイトル | 英語版のダウンロード | 日付 | |||
|---|---|---|---|---|---|---|
| 証明書 | CDCLVP1102EVM EU Declaration of Conformity (DoC) | 2019年 1月 2日 | ||||
| EVM ユーザー ガイド (英語) | CDCLVP1102EVM User's Guide | 2009年 7月 9日 |