CDCLVD1204EVM
CDCLVD1204 評估模組
CDCLVD1204EVM
概覽
The CDCLVD1204/CDCLVD2102 are high-performance, low-additive jitter clock buffers. They have twouniversal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1204 only). The devices also feature on-chip bias generators that can provide the LVDS common-mode voltage to the device inputs. The evaluation module (EVM) is designed to demonstrate the electrical performance of the CDCLVD1204 or CDCLVD2102. However, this EVM can also be used for customers interested in the CDCLVD1208 or CDCLVD2104 as well. This fully assembled and factory-tested evaluation board allows complete validation of device functionalities. For optimum performance, the board is equipped with SMA connectors and well-controlled 50-ohm impedance microstrip transmission lines.
特點
- Easy-to-use evaluation board to fan out low-phase noise clocks
- Easy device setup
- Fast configuration
- Control pins configurable through jumpers
- Board powered at 2.5 V
- Single-ended or differential input clocks
- Device supports four LVDS outputs, EVM supports two LVDS outputs
時鐘緩衝器
技術文件
| 類型 | 標題 | 下載最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| 證書 | CDCLVD1204EVM EU Declaration of Conformity (DoC) | 2019/1/2 | ||||
| 使用指南 | Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board | 2010/6/14 |