CDCLVD1204

Name: CDCLVD1204
Brand: TI
SKU: CDCLVD1204
Price: 3.193 USD

現行

低抖動 2 輸入可選 1:4 通用 LVDS 緩衝器

立即訂購

產品規格表

document-pdfAcrobat CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer datasheet (Rev. B) (英文) PDF | HTML

CDCLVD1204

現行

產品規格表

立即訂購

產品詳細資料

Number of outputs

4

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

20

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

Number of outputs

4

Additive RMS jitter (typ) (fs)

171

Core supply voltage (V)

2.5

Output supply voltage (V)

2.5

Output skew (ps)

20

Operating temperature range (°C)

-40 to 85

Rating

Catalog

Output type

LVDS

Input type

LVCMOS, LVDS, LVPECL

VQFN (RGT)

16

9 mm² 3 x 3

2:4 Differential Buffer
Low Additive Jitter: <300 fs RMS in 10-kHz to 20-MHz
Low Output Skew of 20 ps (Maximum)
Universal Inputs Accept LVDS, LVPECL, and LVCMOS
Selectable Clock Inputs Through Control Pin
4 LVDS Outputs, ANSI EAI/TIA-644A Standard Compatible
Clock Frequency: Up to 800 MHz
Device Power Supply: 2.375 V to 2.625 V
LVDS Reference Voltage, V_{AC_REF}, Available for Capacitive Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
- Telecommunications and Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

All other trademarks are the property of their respective owners

2:4 Differential Buffer
Low Additive Jitter: <300 fs RMS in 10-kHz to 20-MHz
Low Output Skew of 20 ps (Maximum)
Universal Inputs Accept LVDS, LVPECL, and LVCMOS
Selectable Clock Inputs Through Control Pin
4 LVDS Outputs, ANSI EAI/TIA-644A Standard Compatible
Clock Frequency: Up to 800 MHz
Device Power Supply: 2.375 V to 2.625 V
LVDS Reference Voltage, V_{AC_REF}, Available for Capacitive Coupled Inputs
Industrial Temperature Range: –40°C to 85°C
Packaged in 3 mm × 3 mm, 16-Pin VQFN (RGT)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
- Telecommunications and Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

All other trademarks are the property of their respective owners

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, V_{AC_REF}, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.

The CDCLVD1204 clock buffer distributes one of two selectable clock inputs (IN0 and IN1) to 4 pairs of differential LVDS clock outputs (OUT0 through OUT3) with minimum skew for clock distribution. The CDCLVD1204 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1204 is specifically designed for driving 50-Ω transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage, V_{AC_REF}, must be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open, it disables the outputs (static). The part supports a fail safe function. The device incorporates an input hysteresis which prevents random oscillation of the outputs in the absence of an input signal.

The device operates in 2.5-V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1204 is packaged in small, 16-pin, 3-mm × 3-mm VQFN package.

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重要文件	類型	標題	格式選項	日期
*	Data sheet	CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer datasheet (Rev. B)	PDF \| HTML	2016年 10月 5日
	Application note	Sine to Square Wave Conversion Using Clock Buffers	PDF \| HTML	2024年 9月 3日
	Application note	Clocking Design Guidelines: Unused Pins		2015年 11月 19日
	User guide	Low-Additive Jitter, Four LVDS Outputs Clock Buffer Evaluation Board		2010年 6月 14日

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CDCLVD1204EVM — CDCLVD1204 評估模組

The CDCLVD1204/CDCLVD2102 are high-performance, low-additive jitter clock buffers. They have twouniversal input buffers that support single-ended or differential clock inputs and are selectable through a control pin (for CDCLVD1204 only). The devices also feature on-chip bias generators that can (...)

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CDCLVD1204 IBIS Model (Rev. B)

SLLM089B.ZIP (14 KB) - IBIS Model

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封裝	針腳	CAD 符號、佔位空間與 3D 模型
VQFN (RGT)	16	Ultra Librarian

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CDCLVD1204

低抖動 2 輸入可選 1:4 通用 LVDS 緩衝器

CDCLVD1204

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