PMP7977
具有 PMBus 電源管理的 Xilinx Artix 7 FPGA 參考設計
PMP7977
概覽
The Artix 7 power management reference design board uses power modules, linear regulators, and a PMBus compliant system controller to supply all required core and auxiliary voltages needed by the FPGA, including DDR memory termination. A Digital Power graphical user interface is used to monitor the voltage and current levels of the board’s power rails.
特點
- Design optimized to support a 12V input
- 2 PMBus controllers monitors a total of 9 voltage rails
- Solution contains power modules providing up to 6A output current
- Low-noise LDOs provide power for transcievers
- DDR Memory provides volatile synchronous dynamic random access memory to store user code and data
- Design has been built and tested. Reference board is available from Xilinx
| 輸出電壓選項 | PMP7977.1 |
|---|---|
| Vin (最小值) (V) | 4.5 |
| Vin (最大值) (V) | 14 |
| Vout (Nom) (V) | 1 |
| Iout (最大) (A) | 10 |
| 輸出功率 (W) | 10 |
| 隔離式/非隔離式 | Non-Isolated |
| 輸入類型 | DC |
| 拓撲結構 | Buck- Synchronous |
已開發完全組裝的電路板，僅供測試與性能驗證，且為非賣品。
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| 類型 | 標題 | 下載最新的英文版本 | 日期 | |||
|---|---|---|---|---|---|---|
| * | 測試報告 | TI Power Reference Design for Xilinx® Artix®-7 (AC701) | 2014/5/12 | |||
| * | 測試報告 | PMP7977 Test Results (Rev. A) | 2014/6/11 | |||
| 使用指南 | PMP7977 User's Guide | 2013/9/11 |