SAR ADCs are typically limited to sample rates of 10 to 20 MSPS. This webinar will introduce a new family of SAR ADCs with sample rates of 0.5 M to 125 MSPS at 14-bit, and 0.5 M to 65 MSPS at 16 and 18-bit. The 18-bit devices sampling at 65 MSPS are >4X faster than the closest competitive device. Faster sample rates enable; higher frequency signals to be sampled, SNR improvements through oversampling and decimation, and relaxation of anti-alias filter requirements, thereby reducing component count and PCB size.

In this webinar, we will cover:

• Introduction to new family of 14, 16 & 18-bit SAR ADCs.
• Overview of key specifications and features
• Using internal decimation filter to improve SNR
• Anti-alias filter relaxation
• Evaluation board FFT measurements